KAVUAKA Hearing Aid Processor Chip has arrived
The KAVUAKA hearing aid processor developed as part of the Cluster of Excellence "Hearing4all" has arrived as a chip at the Institute for Microelectronic Systems. The KAVUAKA processor is an application-specific instruction set processor (ASIP). The generic basic processor architecture was tested, adapted and optimized using the algorithms developed within the Cluster of Excellence [1,2]. Notable optimizations and extensions include a multiply-accumulate unit (MAC) that handles both real and complex numbers, architectures for power-optimized accesses and an audio interface optimized for low latency.
The highly specialized chip (ASIC) was designed as System-on-Chip (SoC). The SoC consists of four differently optimized versions of the KAVUAKA processor and 10 additional co-processors. These can be activated separately or simultaneously to increase computing power or minimize power dissipation. The chip technology provided by EUROPRACTICE is designed for low power dissipation and has a feature size of 40 nm. The chip is about 3.6 mm2 in size and the power consumption is a few thousandths of a watt.
 Gerlach, L.; Marquardt, D.; Payá Vayá, G.; Liu, S.; Weißbrich, M.; Doclo, S.; Blume, H. (2017): Analyzing the Trade-Off between Power Consumption and Beamforming Algorithm Performance using a Hearing Aid ASIP, 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVII), IEEE DOI: 10.1109/SAMOS.2017.8344615
 Seifert, C.; Thiemann, J.; Gerlach, L.; Volkmar, T.; Payá-Vayá, G.; Blume, H.; van de Par, S. (2017): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a VLIW-SIMD Processor, International Conference on Multimedia and Expo (ICME) 2017, IEEE DOI: 10.1109/ICME.2017.8019478