|Supervisor:||Jun.-Prof. Dr.-Ing. G. Payá-Vayá|
|Researcher:||M. Sc. Florian Giesemann|
|Funded by:||Wege in die Forschung II|
Over the past years, the research field of embedded systems has expanded to include a wide variety of applications, ranging from multimedia portable devices to sensor networks and medical imaging systems. Many of these applications have stringent processing performance requirements and demand for ever smaller and lower power consumption processing systems. All these design constraints in combination with the increasing demand for low cost and time-to-market products make the research field of embedded systems challenging.
In order to meet the abovementioned design goals of a cost- and energy-efficient high-performance embedded system, specialization to a small set of applications is needed. This can be done by inserting special instructions to a processor or by implementing dedicated hardware macros. Nowadays, the preferred way of implementing these kinds of embedded systems is in the form of an application specific integrated circuit (ASIC). But, the functionality, flexibility and processing performance of the resulting ASIC keep unfortunately fixed after the implementation. Therefore, in order to adapt these architectures to future changes in the applications, the architecture will need to be re-designed and re-implemented, resulting in long time-to-market and high production costs.
This project proposes the use of reconfigurable computing techniques provided by current field programmable gate array (FPGA) devices to avoid the necessity of completely re-implementing the embedded multimedia processing system physically every time a new enhanced functionality (i.e. more processing performance) is required. Therefore, instead of implementing “static” ASICs, a new (re-)configurable multimedia soft-processor architecture, hereafter called TUKUTURI, is proposed. The dynamic reconfiguration capability provided by this architecture can be used in run-time to optimize the instruction-set and some parts of the architecture to efficiently execute any kind of multimedia task. In order to evaluate the hardware cost and processing performance trade-offs introduced by this new computer architecture paradigm, a comprehensive environment will be implemented, which includes: (1) an optimized (re-)configurable soft-processor architecture, (2) a complete software toolchain that supports the mentioned reconfiguration capabilities, and (3) two evaluation FPGA-based systems with two different Xilinx FPGA devices to evaluate the performance improvements. In order to perform a fair evaluation, three video-based processing algorithms with different data processing characteristics will be used.
The Institute of Microelectronic Systems (IMS) has a long tradition of designing heterogeneous multi-core systems and application-specific instruction-set processors. The proposed project will combine the knowledge obtained during a previous research project with a completely new dynamically and statically reconfigurable soft-processor architecture paradigm. The resulting architecture will open a new research line in the computer architecture field to meet the high-intensive processing needs of current and future high-performance embedded systems. Therefore, it is also planned to contact other European research groups for future collaborations by actively participating in the HiPEAC-reconfigurable computing research cluster.
Nolting, S.; Vaya, P.; Blume, H. (2011): Optimizing VLIW-SIMD Processor Architectures for FPGA Implementation, ICT.OPEN 2011 Conference (Veldhoven, Netherlands), USB-Proceedings
Giesemann, F.; Payá-Vayá, G.; Blume, H. (2012): A Hardware/Software Environment for Specializing Dynamic Reconfigurable Generic VLIW-SIMD ASIP Architecture, ICT.OPEN 2012 Conference
Payá-Vayá, G.; Burg, R.; Blume, H. (2012): Dynamic Data-Path Self-Reconfiguration of a VLIW-SIMD Soft-Processor Architecture, Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) in conjunction with the 2012 International Conference on Field Programmable Logic and Applications (FPL 2012), (26-29)