Laboratory Mechatronics II: FPGA Prototyping
The goal of these student lab exercises is the design of basic digital circuitry by using the hardware description language VHDL and its emulation on an FPGA prototyping board. Fundamental VHDL skills are taught and the basic methodology for implementing algorithms on an FPGA prototyping board is presented. The processing results are visualized using a graphical user interface (GUI), which is also used for verification of the students projects.
The project tasks are normally carried out in a group of 2 persons at fixed lab times (4 hours each).
The laboratory includes two exercises:
1. Exercise: Seconds counter with decimal output on a 7-segment display
2. Exercise: Finite State Machine (FSM) - traffic lights and coin change
Registration for the FPGA Prototyping laboratory exercises is organized within the Masterlabor Mechatronik II.
The date of the introductory event is given by the organization staff for the Masterlabor Mechatronik II. The participation at the introductory event is mandatory.
The lab notes will be distributed at the introductory event. They are also available at Stud.IP (event name: "Masterlabor Mechatronik II").