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Logo: Institute of Microelectronic Systems
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Logo: Institute of Microelectronic Systems
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Completed Project

Processor Architectures

TETRACOM

Bild zum Projekt TETRACOM

Supervisor:

Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Researcher:

Dipl.-Ing. S. Nolting, Dipl.-Ing. L. Gerlach

Duration:

January 2016 - July 2016

Brief description:

Nowadays, continuous development of digital signal processing applications, e.g., video-based advanced driver assistance systems, are pushing the limits of existing embedded systems and are forcing system developers to spend more time on code optimization. These applications often involve complex mathematical functions like trigonometric, logarithmic, exponential, or square root operations. In particular, these functions can only efficiently be computed on standard general purpose embedded processors, using highly optimized, processor specific arithmetic evaluation software libraries. Another alternative is to extend the embedded processor architectures with a specific hardware accelerator.

 

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Design of a Configurable, Massive-Parallel Vector Processor Architecture for Computer Vision and a Framework for the Implementation of Object Recognition Applications for Embedded Systems

Bild zum Projekt Entwurf einer konfigurierbaren, massiv parallelen Computer-Vision Vektorprozessorarchitektur und einer Abbildungsmethodik für Anwendungen zur Objekterkennung auf eingebetteten Systemen

Supervisor:

Jun.-Prof. Dr.-Ing. Guillermo Payá Vayá

Researcher:

Dipl.-Ing. S. Nolting, Dipl.-Ing. L. Gerlach

Duration:

Mai 2016 - Oktober 2017

Brief description:

The increasing complexity of current computer vision algorithms for autonomous driving, such as object detection and classification using neural networks, represents a challenge for automotive system designers. Providing a real-time processing system under hard real-time constraints and a low energy (budget a few watts) is difficult to achieve even with current technical platforms. The goal of this project is to design a new approach of application-specific vector processor for FPGA implementation. The well-known overhead of other platforms (e.g. GPUs) shall be avoided by using several strategies: Novel functional mechanisms, a modular and customizable architecture and a suitable development framework, which is especially designed for the implementation of automotive applications.). An FPGA-based prototype will demonstrate the performance of the vector processor concept for a selected application at the end of the project.

 

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OPARO

Bild zum Projekt OPARO

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Wirtsch.-Ing. Sebastian Hesselbarth

Brief description:

In the development of integrated, programmable circuits, the optimization of power dissipation and temperature distribution is becoming increasingly important. So far, however, these can only be determined by very time-consuming simulations. Therefore, precise models for the determination of power dissipation shall be developed and mapped together with the functional emulation on FPGAs. By accelerating the determination of power dissipation and temperature distribution, specific optimizations of the architecture and the application code can then be made taking real input data into account.

 

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GEBO - High Temperature Electronic

Bild zum Projekt GEBO - Hochtemperaturelektronik

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Ing. Rochus Nowosielski

Duration:

2009-20111

Brief description:

In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.

 

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High Temperature Measurement While Drilling

Bild zum Projekt High Temperature Measurement While Drilling

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Ing. Rochus Nowosielski

Duration:

2012-2014

Brief description:

The goal of the research is an MWD processor system for drilling tools used for geothermal drilling in ambient temperatures up to 300 °C. The processing of the project includes research aspects in the fields of hardware design, fault tolerance of digital systems and ASIC design.

 

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Biomedical Engineering

TETRACOM - Mobile platform for real-time sonification of movements for medical rehabilitation

Bild zum Projekt TETRACOM - Mobile platform for real-time sonification of movements for medical rehabilitation

Supervisor:

Prof. Dr.-Ing. Holger Blume

Researcher:

M.Sc. Daniel Pfefferkorn

Duration:

September 2013 - August 2016

Funded by:

FP7 ‐ ICT ‐ 2013 ‐ 10

Brief description:

The rehabilitation of stroke patients is an intense and lengthy process. The common therapy approach is based on movement training in presence of a therapist. Through many repetitions a remobilization of the patient is achieved. Due to this highly time‐consuming treatment, the costs of for the therapy are very high. Therefore, in this research project, we are focusing on the design of a mobile system, which will provide a motion feedback by means of sonification. It will enable therapist‐independent training and as a result lessen the strain on patient and healthcare system.

 

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Real-time, low-latency sonification of complex movements

Bild zum Projekt Echtzeitfähige Sonifikation komplexer Bewegungen

Supervisor:

Prof. Dr.-Ing. Blume

Researcher:

Dipl.-Ing. (FH) H.-P. Brückner

Duration:

February 2011 - June 2013

Funded by:

Europäischer Fonds für regionale Entwicklung (EFRE)

Brief description:

The goal of this research project in the field of biomedical engineering is to generate an auditory feedback (sonification) of human movements. The IMS focuses on examing the performance of different hardware platforms for this application. Relevant performance parameters are the platforms power dissipation and the overall latency. Finally, the project goal is to enhance stroke rehabilitation by additionally providing auditory arm movement feedback. This could lead to shortened rehabilitation periods. Furthermore, the mobile hardware platform developed at the IMS allows home based rehabilitation.

 

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Analog/Mixed-Signal-Design

Solving methods for semi-symbolic analog simulation

Bild zum Projekt Lösungsverfahren für semi-symbolische Analog-Simulationen

Supervisor:

Prof. Dr.-Ing. Erich Barke

Researcher:

Dipl.-Ing. Oliver Scharf

Duration:

January 2012 - May 2015

Brief description:

Parameters of analog circuits are not exactly known as they are influenced by fabrication, aging or environment temperature. At the Institute of Microelectronic Systems an analog circuit simulator was developed which use affine arithmetic to simulate these parameter deviations. This project aims at increasing the convergence area by using parameter splitting.

 

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ROBUST

Bild zum Projekt ROBUST

Supervisor:

Prof. Dr.-Ing. Erich Barke

Researcher:

Dipl.-Ing. Michael Kaergel

Duration:

Mai 2009 - April 2012

Funded by:

BMBF

Brief description:

ROBUST researches new methods and procedures for designing robust nanoelectronic systems. The project defines quantitative measures of robustness. These metrics are determined by abstracting models of robustness and by applying new analysis methods suitable for the system level.

 

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Reliable Behavioural Modelling

Bild zum Projekt Verlässliche Modellierung

Supervisor:

Prof. Dr.-Ing. Erich Barke

Researcher:

Dipl.-Ing. Anna Krause

Brief description:

This project aims at generating behavioural models which include parameter variations of the original circuit. Parameter variations are represented by affine arithmetic.

 

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GEBO - High Temperature Electronic

Bild zum Projekt GEBO - Hochtemperaturelektronik

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Ing. Rochus Nowosielski

Duration:

2009-20111

Brief description:

In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.

 

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ANCONA: Analog Mixed-Level Modeling with Accelerated Mixed-Signal Simulation to Increase Analog Coverage

Bild zum Projekt ANCONA: Analoge Mixed-Level-Modellierung mit beschleunigter Mixed-Signal-Simulation zur Erhöhung der Analog-Coverage

Supervisor:

Dr.-Ing. Markus Olbrich

Researcher:

Dipl.-Ing. Lukas Lee

Duration:

Juli 2014 - Juni 2017

Funded by:

BMBF

Brief description:

The IMS develops method and measures for the analysis of analog verification coverage. The goal is to evaluate and to increase the verification coverage of analog and mixed-signal circuits.

 

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Design Space Exploration

OPARO

Bild zum Projekt OPARO

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Wirtsch.-Ing. Sebastian Hesselbarth

Brief description:

In the development of integrated, programmable circuits, the optimization of power dissipation and temperature distribution is becoming increasingly important. So far, however, these can only be determined by very time-consuming simulations. Therefore, precise models for the determination of power dissipation shall be developed and mapped together with the functional emulation on FPGAs. By accelerating the determination of power dissipation and temperature distribution, specific optimizations of the architecture and the application code can then be made taking real input data into account.

 

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EFdiS – Use of airborne SAR with digital interface

Bild zum Projekt EFdiS – Einsatz von Flug-SAR mit digitaler Schnittstelle

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Ing. M. Wielage

Duration:

October 2012 - December 2014

Brief description:

The goal of this research project is the processing of FMCW sensor signals. The first step is intended to digitize the analog data on board through a suitable expansion card. In the second step, the digitized data is to be processed on board, and thus converted to an aerial image.

 

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Physical Design

Untersuchung zur Simulation von Bauelementen und Komponenten für die Entwicklung strahlenrobuster autonomer Systeme

 

Supervisor:

PD Dr.-Ing. Dipl.-Phys. Kirsten Weide-Zaage

Duration:

01.02.2015-31.12.2017

Brief description:

Im Zuge der Miniaturisierung moderner integrierter Schaltungen verändert sich die Strahlenhärte der Systeme und Komponenten. Daraus resultierend ist es notwendig, die die Strahlenhärte beeinflussenden Mechanismen im Halbleiter zu bestimmen.

 

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NEEDS

Bild zum Projekt NEEDS

Supervisor:

Dr.-Ing. Markus Olbrich

Researcher:

M. Sc. Artur Quiring

Duration:

2010 - 2013

Funded by:

The project NEEDS is funded by the Bundesministerium für Bildung und Forschung (BMBF).

Brief description:

Highly integrated electronic systems with heterogeneous components enable reduction of resources and cost. To further benefit from the potential of electronic systems, NEEDS has the goal to advance the research in designing a new class of electronic systems, where several dies are stacked above each other (three-dimensional integrated circuits).

 

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3D-Floorplanning

Bild zum Projekt 3D-Floorplanning

Supervisor:

Markus Olbrich

Researcher:

M. Sc. Artur Quiring

Brief description:

The main goal of this research project is to find appropriate optimization algorithms and datastructures for 3D-Floorplanning. Furthermore, new relevant optimization goals should be identified and analysed.

 

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RESCAR 2.0

Bild zum Projekt RESCAR 2.0

Supervisor:

Prof. Dr.-Ing. Erich Barke

Researcher:

M.Sc. Carolin Katzschke

Duration:

February 2011 - April 2014

Funded by:

BMBF

Brief description:

The IMS is subcontractor of the Infineon AG and will develop methods to manage domain-overlapping constraints.

 

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Component reliability in high temperature automotive applications (Rely)

Bild zum Projekt Component reliability in high temperature automotive applications (Rely)

Supervisor:

PD Dr.-Ing. Dipl.-Phys. K. Weide-Zaage

Researcher:

Dipl.-Ing. Jörg Kludt

Duration:

01.05.2011-30.04.2013

Brief description:

Thermisch-elektrisch-mechanische Simulation, Degradationsmodellierung auf Device-Level

 

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Simulation of electronic devices and components through the influence of radiation

 

Supervisor:

PD Dr.-Ing. Dipl.-Phys. K. Weide-Zaage

Researcher:

PD Dr.-Ing. Dipl.-Phys. K. Weide-Zaage

Duration:

01.09.2013-31.01.2015

Brief description:

Simulation of electronic devices and components under the influence of radiation

 

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Driver Assistance Systems

THINGS2DO - THIN but Great Silicon 2 Design Objects

Bild zum Projekt THINGS2DO - THIN but Great Silicon 2 Design Objects

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Gregor Schewior, Nicolai Behmann

Duration:

February 2016 - March 2018

Funded by:

Europäische Union, Bundesministerium für Bildung und Forschung

Brief description:

THINGS2DO is an ENIAC project, funded by the European Union and the Federal Ministry of Education and Research. The project aims to develop the new Fully Depleted Silicon On Insulator (FD-SOI) technology and the corresponding tool environment for high efficient and highly integrated circuits. The capabilities of the technology are further demonstrated through a demonstrator in the area of Advanced Driver Assistance Systems (ADAS).

 

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ZIM Dream Chip Technologies GmbH

Bild zum Projekt ZIM Dream Chip Technologies GmbH

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Gregor Schewior, Nicolai Behmann

Duration:

September 2015 - December 2016

Funded by:

Bundesministerium für Wirtschaft und Energie

Brief description:

In cooperation with Dream Chip Technologies GmbH, Garben, Germany, the Institute of Microelectronic Systems develops with funding from the Federal Ministry of Economic Affairs and Energy a camera system with integrated algorithms for high quality real time motion estimation in the area of driver assistance systems.

 

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mDAS - Implementation of a real-time demonstrator for multicore-based driver assistance systems

Bild zum Projekt mDAS - Echtzeit-Demonstrator für multicore-basierte Fahrassistenzsysteme

Supervisor:

Prof. Dr.-Ing. Holger Blume

Researcher:

Dipl.-Ing. Jakob Arndt

Duration:

February 2014 - August 2014

Funded by:

Siemens AG

Brief description:

The goal of this Project is the conceptual design of a real-time mutlicore-based demonstrator for video-based driver assistance algorithms. Therefore, different performance metrics will be displayed in order to compare platform-specific performance characteristics.

 

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ASEV

Bild zum Projekt ASEV

Supervisor:

Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Researcher:

Dipl.-Ing. Nico Mentzer

Duration:

Mai 2010 - April 2013

Funded by:

Bundesministerium für Bildung und Forschung (BMBF)

Brief description:

The goal of this sub-project of the BMBF project "Automatic Situation Interpretation for Event Triggered Video Surveillance" is to elaborate a concept for a hardware architecture that enables a SIFT (Scale Invariant Feature Transform) feature extraction under application-specific processing conditions as performance and power consumption. SIFT features offer a good basis for robust object identification and tracking for event triggered video surveillance. The field of application is thereby the airport apron, which is highly relevant to security. The concept was implemented on a FPGA-based hardware platform to build a demonstrator which was tested at the end of the project at the airport of Braunschweig.

 

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OpenFAS

Bild zum Projekt OpenFAS

Supervisor:

Prof. Dr.-Ing. Holger Blume

Researcher:

Dipl.-Ing. Christopher Bartels

Duration:

Juni 2012 - Oktober 2013

Funded by:

"Zentrales Innovationsprogramm Mittelstand" des Bundesministeriums für Wirtschaft und Technologie (BMWi)

Brief description:

In the scope of this project, a library of modules for driver assistence systems, based on a multicore processor architecture will be created. The project is in collaboration with the videantis corporation.

 

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PROPEDES - Predictive Pedestrian Protection at Night

Bild zum Projekt PROPEDES - Predictive Pedestrian Protection at Night

Supervisor:

Prof. Dr.-Ing. Holger Blume

Researcher:

Dipl.-Ing. Gregor Schewior

Duration:

August 2008 - July 2011

Funded by:

Bundesministerium für Bildung und Forschung (BMBF)

Brief description:

The objectives of the project PROPEDES is the design and demonstration of a flexible hardware archtecture based on a Very Long Instruction Word (VLIW) Softcore microprocessor for a vision-based pedestrian detection. The VLIW processor is to be supported by dedicated hardware accelerators to speed up future high-quality video-based driver assistance systems. Finally the architecture is to be implemented on a real-time FPGA-based demonstrator.

 

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DESERVE - Development Platform for Safe and Efficient Drive

Bild zum Projekt DESERVE - Development Platform for Safe and Efficient Drive

Supervisor:

Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Researcher:

Florian Giesemann, Frank Meinl, Nico Mentzer

Duration:

September 2012 - August 2015

Funded by:

Europäische Union, Bundesministerium für Bildung und Forschung

Brief description:

DESERVE is a project funded by the European Union. The aim of the project is the promotion and evolution of advanced driver assistance systems (ADAS). These systems are devoted to support the driver in the safe control of the vehicle. For this purpose, the DESERVE platform is planned to be developed. This platform will be the base for future development of advanced driver assistance systems in Europe.

 

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Efficient Hardware Architectures for Fast Image Sequence Analysis

 

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Julian Hartig

Duration:

February 2014 - February 2017

Funded by:

Hans L. Merkle Stiftung

Brief description:

In practice, general reliability of modern driver assistance systems under arbitrary traffic, weather and illumination conditions often is a problem. Because more robust algorithms are computationally very intensive, this project deals with the examination of heterogenous hardware architectures and the evaluation of new mechanisms for complex applications in the field of camera-based driver assistance.

 

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Reconfigurable Architectures

Design of a Configurable, Massive-Parallel Vector Processor Architecture for Computer Vision and a Framework for the Implementation of Object Recognition Applications for Embedded Systems

Bild zum Projekt Entwurf einer konfigurierbaren, massiv parallelen Computer-Vision Vektorprozessorarchitektur und einer Abbildungsmethodik für Anwendungen zur Objekterkennung auf eingebetteten Systemen

Supervisor:

Jun.-Prof. Dr.-Ing. Guillermo Payá Vayá

Researcher:

Dipl.-Ing. S. Nolting, Dipl.-Ing. L. Gerlach

Duration:

Mai 2016 - Oktober 2017

Brief description:

The increasing complexity of current computer vision algorithms for autonomous driving, such as object detection and classification using neural networks, represents a challenge for automotive system designers. Providing a real-time processing system under hard real-time constraints and a low energy (budget a few watts) is difficult to achieve even with current technical platforms. The goal of this project is to design a new approach of application-specific vector processor for FPGA implementation. The well-known overhead of other platforms (e.g. GPUs) shall be avoided by using several strategies: Novel functional mechanisms, a modular and customizable architecture and a suitable development framework, which is especially designed for the implementation of automotive applications.). An FPGA-based prototype will demonstrate the performance of the vector processor concept for a selected application at the end of the project.

 

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Circuit Design and Physical Design for a Novel FPGA Architecture

Bild zum Projekt Schaltungsentwurf und physikalisches Design für eine neuartige FPGA-Architektur

Supervisor:

Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Researcher:

B. Bredthauer, C. Spindeldreier

Duration:

May 2013 - June 2014

Funded by:

Federal Ministry of Education and Reserach

Brief description:

Evaluation and analysis of the implemtability and performance of a new type of field programmable gate array (FPGA).

 

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System Design

TETRACOM - Mobile platform for real-time sonification of movements for medical rehabilitation

Bild zum Projekt TETRACOM - Mobile platform for real-time sonification of movements for medical rehabilitation

Supervisor:

Prof. Dr.-Ing. Holger Blume

Researcher:

M.Sc. Daniel Pfefferkorn

Duration:

September 2013 - August 2016

Funded by:

FP7 ‐ ICT ‐ 2013 ‐ 10

Brief description:

The rehabilitation of stroke patients is an intense and lengthy process. The common therapy approach is based on movement training in presence of a therapist. Through many repetitions a remobilization of the patient is achieved. Due to this highly time‐consuming treatment, the costs of for the therapy are very high. Therefore, in this research project, we are focusing on the design of a mobile system, which will provide a motion feedback by means of sonification. It will enable therapist‐independent training and as a result lessen the strain on patient and healthcare system.

 

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Site-optimized Wireless Communication Architectures

Bild zum Projekt Gebäude-optimierte Funkkommunikationsarchitekturen

Supervisor:

Prof. Dr.-Ing. Holger Blume

Researcher:

M.Sc. Daniel Pfefferkorn

Brief description:

The communication parameters to be expected in an application scenario result from the combination of the employed standards' properties (IEEE 802.11, BLE, IEEE 802.154, ZigBee) and the specific radio wave propagation conditions of the considered building.

 

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GEBO - High Temperature Electronic

Bild zum Projekt GEBO - Hochtemperaturelektronik

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Ing. Rochus Nowosielski

Duration:

2009-20111

Brief description:

In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.

 

| details |