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Logo: Institute of Microelectronic Systems
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Application-Specific Instruction-Set Processors

Jun-Prof. Dr.-Ing. Guillermo Payá Vayá, Prof. Dr.-Ing. Holger Blume

Lectures

Start of the lecture: 18.10.2018
Extent: 2 lecture hours + 1 exercise hours + 1 block excercise (5 CP)
Thursdays, 9:30 - 11:00
Room 335, TI-Building (3703)

Exercises

Thursdays, 11:15 - 12:30 (including first lecture date!)
Room 335, TI-Building (3703)

Contact: asipims.uni-hannover.de

Exam

Oral examination, 30 minutes.

Recommended prior knowledge

Please note

This lecture is held in English. It is designed for master course students.

Content

  • Fundamentals of Computer Design
    Definition of computer architecture. Computer architecture classifications. Trends in Technology (Moore Law, Amdahl’s Law,…)
  • Pipelined/Non-pipelined Processors
    Datapath and control. Overview of pipelining. Data hazards, forwarding, and stalls. Control hazards. Basic compiler techniques.
  • Instruction-Level Parallelism
    Concepts and challenges. Superscalar and VLIW processors. Static vs. Dynamic scheduling. Basic compiler techniques for exposing ILP. Hardware implications.
  • Data-Level Parallelism
    Single Instruction Multiple Data (SIMD) architectures. Vector Processors. Compiler techniques. Hardware implications.
  • Application-Specific Instruction-Set Processor (ASIP)
    Customizable processors. Benefits of processor customizations. Profiling methods.
  • Computer Arithmetic I
    Conventional number systems. Fast additions. High-speed multiplication. Fast division.
  • Computer Arithmetic II
    Evaluation of elementary functions: exponential, logarithm, trigonometric,...
  • Memory Systems
    Memory-system organization and operation. Cache mechanism vs. direct memory access (DMA) controller. Hardware implications.
  • Thread-Level Parallelism
    Multithreading to improve single-core processor throughput. Software and Hardware mechanisms. Distributed shared-memory and coherency. Parallel programming.
  • Graphic Processing Units and Massively Parallel Processors
  • Heterogeneous/Homogeneous Multi-Core Systems.
  • Reconfigurable Processor Architectures.

Please see the StudIP portal for more information.