Forschung
Publikationen Mixed-Signal-Schaltungen

Publikationen des Fachgebiets Mixed-Signal-Schaltungen

Konferenzbeiträge

  • Kochdumper, N.; Tarraf, A.; Rechmal, M.; Olbrich, M.; Hedrich, L.; Althoff, M. (2020): Establishing Reachset Conformance for the Formal Analysis of Analog CircuitsProceedings APSDAC 2020
    DOI: 10.1109/ASP-DAC47756.2020.9045120
  • Kaufmann, M.; Seidel, A.; Wicht, B. (2020): Long, Short, Monolithic-The Gate Loop Challenge for GaN DriversIEEE Custom Integrated Circuits Conference (CICC)
    DOI: 10.1109/CICC48029.2020.9075937
  • Rindfleisch, C.; Wicht, B. (2020): 11.3 A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency2020 IEEE International Solid- State Circuits Conference - (ISSCC)
    DOI: 10.1109/ISSCC19947.2020.9063150
  • Kaufmann, M.; Lueders, M.; Cetin, K.; Wicht, B. (2020): 18.2 A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency2020 IEEE International Solid- State Circuits Conference - (ISSCC)
    DOI: 10.1109/ISSCC19947.2020.9063102
  • Wicht, B. (2020): T2: Analog Building Blocks of DC-DC Converters2020 IEEE International Solid- State Circuits Conference - (ISSCC)
    DOI: 10.1109/ISSCC19947.2020.9062975
  • Chae, Y.; Wicht, B.; Verbruggen, B.; Heydari, P.; Luong, H. (2019): Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)IEEE Journal of Solid-State Circuits ( Volume: 54 , Issue: 12 , Dec. 2019 )
    DOI: 10.1109/JSSC.2019.2946496
  • Olorunfemi Ojo, J. (2019): Best Papers and Star Associate Editors (2018)IEEE Journal of Emerging and Selected Topics in Power Electronics ( Volume: 7 , Issue: 4 , Dec. 2019 )
    DOI: 10.1109/JESTPE.2019.2943771
  • Renz, P.; Kaufmann, M.; Lueders, M.; Wicht, B. (2019): A 3-Ratio 85% Efficient Resonant SC Converter With On-Chip Coil for Li-Ion Battery OperationIEEE Solid-State Circuits Letters ( Volume: 2 , Issue: 11 , Nov. 2019 )
    DOI: 10.1109/LSSC.2019.2927131
  • Kiesel, S.; Kern, T.; Wicht, B.; Graeb, H. (2019): A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
    DOI: 10.1109/VLSI-DAT.2019.8741536
  • Funk, T.; Groeger, J.; Wicht, B. (2019): An Integrated and Galvanically Isolated DC-to-15.3 MHz Hybrid Current Sensor2019 IEEE Applied Power Electronics Conference and Exposition (APEC)
    DOI: 10.1109/APEC.2019.8722098
  • Quenzer-Hohmuth, S.; Messner, J.; Ritzmann, S.; Rosahl, T.; Wicht, B. (2019): Accelerated Low Gate Count Parameter Identification for Integrated Switched-Mode Power Supplies with Digital Control2019 IEEE Applied Power Electronics Conference and Exposition (APEC)
    DOI: 10.1109/APEC.2019.8722002
  • Renz, P.; Kaufmann, M.; Lueders, M.; Wicht, B. (2019): 8.6 A Fully Integrated 85%-Peak-Efficiency Hybrid Multi Ratio Resonant DC-DC Converter with 3.0-to-4.5V Input and 500μA -to-120mA Load Range2019 IEEE International Solid- State Circuits Conference - (ISSCC)
    DOI: 10.1109/ISSCC.2019.8662491
  • Divanbeigi, S.; Aditya, E.; Wang, Z.P.; Olbrich, M. (2019): Enabling Complex Stimuli in Accelerated Mixed-Signal Simulation56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, United States. Weitere Informationen
    DOI: 10.1145/3316781.3317815
    ISBN: 9781450367257
  • Divanbeigi, S.; Winkler, F.; Bergen, M.; Olbrich, M. (2018): Modeling And Accelerated Mixed-Signal Simulation Of A Control System21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS, pp. 95-100 Weitere Informationen
    DOI: 10.1109/DDECS.2018.00024
  • Bredthauer, B.; Olbrich, M.; Barke, E. (2018): Parallelization Strategies for the Detailed Routing StepAnalog 2018; 16th GMM/ITG-Symposium, VDE
    ISBN: 978-3-8007-4754-2
  • Seidel, A.; Wicht, B. (2018): Integrated Gate Drivers Based on High-Voltage Energy Storing for GaN TransistorsIEEE Journal of Solid-State Circuits ( Volume: 53 , Issue: 12 , Dec. 2018 )
    DOI: 10.1109/JSSC.2018.2866948
  • Lutz, D.; Seidel, A.; Wicht, B. (2018): A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC ConvertersESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)
    DOI: 10.1109/ESSCIRC.2018.8494292
  • Quenzer-Hohmuth, S.; Ritzmann, S.; Rosahl, T.; Wicht, B. (2018): A Boost Converter with 3-6V Input and Fast Transient Digital Control Comprising a 90 ns-Latency Live-Tracking Window ADCESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)
    DOI: 10.1109/ESSCIRC.2018.8494242
  • Wittmann, J.; Funk, T.; Rosahl, T.; Wicht, B. (2018): A 48-V Wide- Vin 9–25-MHz Resonant DC–DC ConverterIEEE Journal of Solid-State Circuits ( Volume: 53 , Issue: 7 , July 2018 )
    DOI: 10.1109/JSSC.2018.2827953
  • Funk, T.; Wicht, B. (2018): A fully integrated DC to 75 MHz current sensing circuit with on-chip Rogowski coil2018 IEEE Custom Integrated Circuits Conference (CICC)
    DOI: 10.1109/CICC.2018.8357028
  • Quenzer-Hohmuth, S.; Ritzmann, S.; Rosahl, T.; Wicht, B. (2018): ΔV/Δt-intervention control concept for improved transient response in digitally controlled boost converters2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    DOI: 10.1109/APEC.2018.8341029
  • Santoro, F.; Kuhn, R.; Gibson, N.; Rasera, N.; Tost, T.; Graeb, H.; Wicht, B.; Brederlow, R. (2018): A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC ApplicationsIEEE Journal of Solid-State Circuits ( Volume: 53 , Issue: 6 , June 2018 )
    DOI: 10.1109/JSSC.2018.2799964
  • Thomsen, A.; Wicht, B.; Harpe, P.; Kay Law, M.; Cheol Chae, Y. (2018): F6: Advances in energy efficient analog design2018 IEEE International Solid - State Circuits Conference - (ISSCC)
    DOI: 10.1109/ISSCC.2018.8310408
  • Seidel, A.; Wicht, B. (2018): A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors2018 IEEE International Solid - State Circuits Conference - (ISSCC)
    DOI: 10.1109/ISSCC.2018.8310345
  • Lutz, D.; Renz, P.; Wicht, B. (2018): An Integrated 3-mW 120/230-V AC Mains Micropower SupplyIEEE Journal of Emerging and Selected Topics in Power Electronics ( Volume: 6 , Issue: 2 , June 2018 )
    DOI: 10.1109/JESTPE.2018.2798504
  • Bredthauer, B.; Olbrich, M.; Barke, E. (2018): STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units17th International Symposium on Parallel and Distributed Computing, ISPDC, pp. 77-84 Weitere Informationen
    DOI: 10.1109/ISPDC2018.2018.00020
  • Fürtig, A.; Hedrich, L.; Hartong, W.; Tanguay, L.-F.; Olbrich, M.; Rechmal, M. (2018): Coverage Measures and a Unified Coverage Model for Analog Circuit DesignANALOG 2018; 16th GMM/ITG-Symposium, Munich/Neubiberg, Germany, pp. 74-79. Weitere Informationen
    ISBN: 978-3-8007-4754-2
  • Divanbeigi, S.; Aditya, E.; Olbrich, M. (2017): Accelerated Mixed-Signal Simulations Using Multi-Core ArchitectureFrontiers in Analog CAD Weitere Informationen
    ISBN: 978-3-8007-4442-8
  • Wittmann, J.; Funk, T.; Rosahl, T.; Wicht, B. (2017): A 12–48 V wide-vin 9–15 MHz soft-switching controlled resonant DCDC converterESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
    DOI: 10.1109/ESSCIRC.2017.8094597
  • Kiesel, S.; Kern, T.; Wicht, B. (2017): Time-domain ramped gate sensing for embedded multi-level flash in automotive applications2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
    DOI: 10.1109/MWSCAS.2017.8053017
  • Groeger, J.; Wicht, B.; Norling, K. (2017): Dynamic stability of a closed-loop gate driver enabling digitally controlled slope shaping2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
    DOI: 10.1109/PRIME.2017.7974107
  • Groeger, J.; Schindler, A.; Wicht, B.; Norling, K. (2017): Optimized dv/dt, di/dt sensing for a digitally controlled slope shaping gate driver2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
    DOI: 10.1109/APEC.2017.7931209
  • Schindler, A.; Koeppl, B.; Wicht, B.; Groeger, J. (2017): 10ns Variable current gate driver with control loop for optimized gate current timing and level control for in-transition slope shaping2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
    DOI: 10.1109/APEC.2017.7931210
  • Seidel, A.; Wicht, B. (2017): 25.3 A 1.3A gate driver for GaN with fully integrated gate charge buffer capacitor delivering 11nC enabled by high-voltage energy storing2017 IEEE International Solid-State Circuits Conference (ISSCC)
    DOI: 10.1109/ISSCC.2017.7870446
  • Renz, P.; Lamprecht, P.; Teufel, D.; Wicht, B. (2017): A 40V current sensing circuit with fast on/off transition for high-voltage power management2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)
    DOI: 10.1109/MWSCAS.2016.7870011
  • Furtig, A.; Glaeser, G.; Grimm, C.; Hedrich, L.; Heinen, S.; Lee, H.-S. L.; Nitsche, G.; Olbrich, M.; Radojicic, C.; Speicher, F. (2017): Novel Metrics for Analog Mixed-Signal Coverage20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
    DOI: 10.1109/DDECS.2017.7934589
  • Divanbeigi, S.; Lee, H.-S. L.; Röhrig E.; Olbrich, M.; Barke E. (2016): Modeling of Linear Stimuli for Accelerated Mixed-Signal Simulations15. ITG/GMM Fachtagung ANALOG 2016, Verifikation von Schaltungen und Systemen für das Internet der Dinge, Bremen, Germany Weitere Informationen
    ISBN: 978-3-8007-4265-3
  • Barke, E.; Fürtig, A.; Gläser, G.; Grimm, C.; Hedrich, L.; Heinen, S.; Hennig, E.; Lee H.-S. L.; Nebel, W.; Nitsche, G.; Olbrich, M.; Radojicic, C.; Speicher, F. (2016): Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Weitere Informationen
  • Hackel, J.; Seidel, A.; Wittmann, J.; Wicht, B. (2016): Capacitive Gate Drive Signal Transmission with Transient Immunity up to 300 V/nsANALOG 2016; 15. ITG/GMM-Symposium
    ISBN: 016 978-3-8007-4265-3
  • Schindler, A.; Koeppl, B.; Pottbaecker, A.; Zannoth, M.; Wicht, B. (2016): Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dipESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
    DOI: 10.1109/ESSCIRC.2016.7598308
  • Lutz, D.; Renz, P.; Wicht, B. (2016): A 120/230 Vrms-to-3.3V micro power supply with a fully integrated 17V SC DCDC converterESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
    DOI: 10.1109/ESSCIRC.2016.7598338
  • Rindfleisch, C.; Wicht, B. (2016): Efficiency impact of air-cored inductors in multi-MHz power converters2016 18th European Conference on Power Electronics and Applications (EPE'16 ECCE Europe)
    DOI: 10.1109/EPE.2016.7695433
  • Quenzer-Hohmuth, S.; Ritzmann, S.; Rosahl, T.; Wicht, B. (2016): Boost converter with load dependent adaptive controller for improved transient response2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
    DOI: 10.1109/PRIME.2016.7519468
  • Wittmann, J.; Barner, A.; Rosahl, T.; Wicht, B. (2016): An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time ControlIEEE Journal of Solid-State Circuits ( Volume: 51 , Issue: 7 , July 2016 )
    DOI: 10.1109/JSSC.2016.2550498
  • Barner, A.; Wittmann, J.; Rosahl, T.; Wicht, B. (2016): A 10 MHz, 48-to-5V synchronous converter with dead time enabled 125 ps resolution zero-voltage switching2016 IEEE Applied Power Electronics Conference and Exposition (APEC)
    DOI: 10.1109/APEC.2016.7467859
  • Lutz, D.; Renz, P.; Wicht, B. (2016): 12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiency2016 IEEE International Solid-State Circuits Conference (ISSCC)
    DOI: 10.1109/ISSCC.2016.7417988
  • Gläser, G.; Lee, H.S. L.; Olbrich, M.; Barke, E. (2016): Knowing your AMS system's limits: system acceptance region exploration by using automated model refinement and accelerated simulationForum on Specification and Design Languages (FDL)
    DOI: 10.1109/FDL.2016.7880383
  • Quiring, A.; Olbrich, M.; Barke, E. (2015): Fast Global Interconnnect Driven 3D FloorplanningVLSI-SoC
    DOI: 10.1109/VLSI-SoC.2015.7314436
  • Lee, H.-S. L.; Olbrich, M.; Barke, E. (2015): Analog Mixed-Level Modeling for Accelerated Simulation to Increase the Analog CoverageFDL 2015, Forum on specification & Design Languages, Barcelona, Special Session "Towards Analog-/Mixed-Signal Coverage"
  • Scharf, O.; Olbrich, M.; Barke, E. (2015): Split and Merge Strategies for Solving Uncertain Equations Using Affine ArithmeticProceedings of the SIMUTOOLS 2015
    DOI: 10.4108/eai.24-8-2015.2260594
  • Schindler, A.; Koeppl, B.; Wicht, B. (2015): EMC and switching loss improvement for fast switching power stages by di/dt, dv/dt optimization with 10ns variable current source gate driver2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)
    DOI: 10.1109/EMCCompo.2015.7358323
  • Wittmann, J.; Barner, A.; Rosahl, T.; Wicht, B. (2015): A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chainESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)
    DOI: 10.1109/ESSCIRC.2015.7313859
  • Wittmann, J.; Wicht, B. (2015): A configurable sawtooth based PWM generator with 2 ns on-time for >50 MHz DCDC converters2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
    DOI: 10.1109/PRIME.2015.7251089
  • Funk, T.; Wittmann, J.; Rosahl, T.; Wicht, B. (2015): A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching2015 IEEE International Symposium on Circuits and Systems (ISCAS)
    DOI: 10.1109/ISCAS.2015.7168990
  • Kilian, M.; Joos, J.; Wicht, B. (2015): A 3.6kW Efficiency and Switching Frequency Improved DC- DC-Converter Design with Optimized Mounting and Interconnect TechnologyProceedings of PCIM Europe 2015; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
    ISBN: 978-3-8007-3924-0
  • Wittmann, J.; Rindfleisch, C.; Wicht, B. (2015): Substrate coupling in fast-switching integrated power stages2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)
    DOI: 10.1109/ISPSD.2015.7123459
  • Lee, H.-S. L.; Althoff, M.; Hoelldampf, S.; Olbrich, M.; Barke, E. (2015): Automated Generation of Hybrid System Models for Reachability Analysis of Nonlinear Analog CircuitsDesign Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, pp.725,730
    DOI: 10.1109/ASPDAC.2015.7059096
    ISBN: 978-1-4799-7790-1
  • Seidel, A.; Salvatore Costa, M.; Joos, J.; Wicht, B. (2015): Area Efficient Integrated Gate Drivers Based on High-Voltage Charge StoringIEEE Journal of Solid-State Circuits ( Volume: 50 , Issue: 7 , July 2015 )
    DOI: 10.1109/JSSC.2015.2410797
  • Seidel, A.; Costa, M.; Joos, J.; Wicht, B. (2015): Isolated 100% PWM gate driver with auxiliary energy and bidirectional FM/AM signal transmission via single transformer2015 IEEE Applied Power Electronics Conference and Exposition (APEC)
    DOI: 10.1109/APEC.2015.7104715
  • Lutz, D.; Renz, P.; Wicht, B. (2015): Low-Power-SC-Wandler mit hoher variabler EingangsspannungMPC / Multi-Projekt-Chip-Gruppe Baden-Württemberg : Tagungsband zum Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg ; 53. Workshop on Microelectronics, 6. Februar 2015, Hochschule Esslingen, Germany
    ISSN: 1868-9221
  • Yasar, I.; Staudt, R.; Jiago Teffo, C.; Schoch, B.; Stoof, T.; Wittmann, J.; Wicht, B. (2015): Flächenoptimierte Bandgap-Referenz für Low-Power- Anwendungen mit 2,5 – 5,5 V Versorgung
  • Krause, Anna; Olbrich, Markus; Barke, Erich (2014): Variation-Aware Behavioral Models of Analog Circuits Using Support Vector Machines with Interval ParametersComputer Science and Electronic Engineering Conference (CEEC), 2014 6th
    DOI: 10.1109/CEEC.2014.6958566
  • Kärgel, M.; Olbrich, M.; Barke, E. (2014): Simulation Based Verification with Range Based Signal Representations for Mixed-Signal SystemsSBCCI
    DOI: 10.1145/2660540.2661010
    ISBN: 978-1-4503-3156-2
  • Krause, A.; Olbrich, M.; Barke, E. (2014): Intervallwertige Support Vector Machines zur Verhaltensmodellierung analoger Schaltungen mit Parametervariationen Tagungsband Analog2014
    ISBN: 978-3-8007-3638-6
  • Katzschke, C.; Sohn, M.-P.; Olbrich, M.; Meyer zu Bexten, V.; Tristl, M.; Barke, E. (2014): Application of Mission Profiles to Enable Cross-Domain Constraint-Driven DesignDATE, 1-6
    DOI: 10.7873/DATE.2014.079
  • Wittmann, J.; Seidel, A.; Wicht, B. (2014): Efficiency modeling for MHz DCDC converters at 40V input voltage range
    DOI: 10.5194/ars-12-111-2014
  • Wittmann, J.; Rosahl, T.; Wicht, B. (2014): A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC convertersESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)
    DOI: 10.1109/ESSCIRC.2014.6942044
  • Seidel, A.; Costa, M.; Joos, J.; Wicht, B. (2014): Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systemsESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)
    DOI: 10.1109/ESSCIRC.2014.6942046
  • Wursthorn, J.; Knapp, H.; Wicht, B. (2014): A millimeter-wave power amplifier concept in SiGe BiCMOS technology for investigating HBT physical limitations
  • Rindfleisch, C.; Wittmann, J.; Wicht, B. (2014): Substratkoppeln in schnell schaltenden integrierten LeistungsendstufenMPC / Multi-Projekt-Chip-Gruppe Baden-Württemberg : Tagungsband zum Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg ; 52. Workshop on Microelectronics, 11. Juli 2014, Hochschule Künzelsau, Germany
    ISSN: 1862-7102
  • Kollmitzer, M.; Olbrich, M.; Barke, E. (2013): Analysis and Modeling of Minority Carrier Injection in Deep-Trench Based BCD Technologies9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2013), (245-248)
    DOI: 10.1109/PRIME.2013.6603160
  • Kärgel, M.; Olbrich, M.; Barke, E. (2013): Verification of Mixed-Signal Systems with Range Based Signal RepresentationsFrontiers in Analog CAD 2013 (FAC 2013)
  • Scharf, O.; Olbrich, M.; Barke, E. (2013): Lösungsverfahren für nichtlineare implizite Gleichungssysteme unter Verwendung von Affiner Arithmetik und Gebietsaufteilungen ANALOG 2-1, VDE-Verlag
    ISBN: 978-3-8007-3467-2
  • Hölldampf, S.; Lee, H.-S. L.; Olbrich, M.; Barke, E. (2013): Generation of Piecewise-Linear Semiconductor Models for Accelerated Mixed-Signal SimulationFrontiers in Analog CAD 2013 (FAC 2013) Weitere Informationen
  • Schindler, A.; Koeppl, B.; Wicht, B. (2013): EMC analysis of current source gate drivers2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)
    DOI: 10.1109/EMCCompo.2013.6735181
  • Wittmann, J.; Wicht, B. (2013): MHz-converter design for high conversion ratio2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)
    DOI: 10.1109/ISPSD.2013.6694445
  • Lin, M.; Huang, Y.; Ehrhart, A.; Lee, Y.; Chiu, C.; Wicht, B.; Chen, K. (2013): Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter2013 IEEE International Symposium on Circuits and Systems (ISCAS)
    DOI: 10.1109/ISCAS.2013.6572498
  • Ehrhart, A.; Wicht, B.; Lin, M.; Huang, Y.; Lee, Y.; Chen, K. (2013): Adaptive pulse skipping and adaptive compensation capacitance techniques in current-mode buck-boost DC-DC converters for fast transient response2013 IEEE 10th International Conference on Power Electronics and Drive Systems (PEDS)
    DOI: 10.1109/PEDS.2013.6527047
  • Gottschling, P.; Rosahl, T.; Wicht, B. (2013): Analyse des SEPIC-Spannungswandlers für Automotive-AnwendungenMPC / Multi-Projekt-Chip-Gruppe Baden-Württemberg : Tagungsband zum Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg : Workshop Juli 2013, Konstanz
    ISSN: 1868-9221
  • Ehrhart, A.; Wicht, B.; Chen, K. (2013): A current-mode buck-boost DC-DC converter with fast transient responseMPC / Multi-Projekt-Chip-Gruppe Baden-Württemberg : Tagungsband zum Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg : Workshop Februar 2013, Mannheim
    ISSN: 1868-9221
  • Barke, M.; Kärgel, M.; Lu, W.; Salfelder, F.; Hedrich, L.; Olbrich, M.; Radetzki, M.; Schlichtmann, U. (2012): Robustness Validation of Integrated Circuits and Systems4th Asia Symposium on Quality Electronic Design (ASQED), 2012 (145-154)
    DOI: 10.1109/ACQED.2012.6320491
  • Krause, A.; Olbrich, M.; Barke, E. (2012): Enclosing the Modeling Error in Analog Behavioral Models Using Neural Networks and Affine ArithmeticInternational Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2012 (SMACD 2012), (5-8)
    DOI: 10.1109/SMACD.2012.6339403
  • Quiring, A.; Lindenberg, M.; Olbrich, M.; Barke, E. (2012): 3D Floorplanning Considering Vertically Aligned Rectilinear Modules Using T∗-treeIEEE International 3D Systems Integration Conference (3DIC), 2-1, (1-5)
    DOI: 10.1109/3DIC.2012.6263030
  • Hölldampf, S.; Lee, H.-S. L.; Zaum, D.; Olbrich, M.; Barke, E. (2012): Efficient Generation of Analog Circuit Models for Accelerated Mixed-Signal SimulationIEEE International System-on-Chip Conference 2012 (SOCC 2012), (104-109)
    DOI: 10.1109/SOCC.2012.6398386
    ISBN: 978-1-4673-1294-3
  • Wittmann, J.; Neidhardt, J.; Wicht, B. (2012): EMC Optimized Design of Linear Regulators Including a Charge PumpIEEE Transactions on Power Electronics ( Volume: 28 , Issue: 10 , Oct. 2013 )
    DOI: 10.1109/TPEL.2012.2232785
  • Hölldampf, S.; Zaum, D.; Neumann, I.; Olbrich, M.; Barke, E. (2011): Fast Mixed-Signal Simulation using SystemCIEEE International Systems Conference 2011 (SysCon 2011)
    DOI: 10.1109/SYSCON.2011.5929046
  • Hinrichs, H.; Olbrich, M.; Barke, E. (2011): Optimization of Chip Design ProcessesAfrican Conference on Software Engineering and Applied Computing
  • Wang, L.; Olbrich, M.; Barke, E.; Buechner, T.; Buehler, M.; Panitz, P. (2011): A Theoretical Probabilistic Simulation Framework for Dynamic Power EstimationThe 2011 International Conference on Computer-Aided Design (ICCAD 2011), (708-715)
    DOI: 10.1109/ICCAD.2011.6105407
  • Scharf, O.; Olbrich, M.; Barke, E. (2011): Anwendung der affinen Arithmetik auf das BSIMSOI-Modell zur Simulation von ParameterschwankungenANALOG 2-1, VDE-Verlag, (S. 49-54)
    ISBN: 978-3-8007-3369-9
  • Hölldampf, S.; Zaum, D.; Olbrich, M.; Barke, E (2011): Using Analog Circuit Behavior to Generate SystemC Events for an Acceleration of Mixed-Signal SimulationIEEE International Conference on Computer Design 2011 (ICCD 2011)
    DOI: 10.1109/ICCD.2011.6081384
  • Wittmann, J.; Wicht, B. (2011): EMC influence of the charge pump in linear regulators - Design, simulation and measurements2011 IEEE International Symposium of Circuits and Systems (ISCAS)
    DOI: 014 10.1109/ISCAS.2011.5937824
  • Schupfer, F.; Kärgel, M.; Grimm, C.; Olbrich, M.; Barke, E. (2010): Towards Abstract Analysis Techniques for Range Based System SimulationsFDL 2-1, (6)
    DOI: 10.1049/ic.2010.0146
  • Zaum, D.; Hölldampf, S.; Neumann, I.; Olbrich, M.; Barke, E. (2010): An Accelerated Mixed-Signal Simulation Kernel for SystemCForum on Specification & Design Languages 2010 (FDL)
    DOI: 10.1049/ic.2010.0158
  • Zaum, D.; Hölldampf, S.; Neumann, I.; Olbrich, M.; Barke, E. (2010): SystemC Mixed-Signal and Mixed-Level Simulation using an Accelerated Analog Simulation ApproachThe International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design 2010 (SM2ACD)
    DOI: 10.1109/SM2ACD.2010.5672303
  • Hinrichs, H.; Olbrich, M.; Barke, E. (2010): Performance Management and Optimization of Semiconductor Design ProjectsIAENG Transactions on Engineering Technologies Volume 4: Special Edition of the World Congress on Engineering and Computer Science 2-1, American Institute of Physics (AIP)
    DOI: 10.1063/1.3460248
  • Hinrichs, H.; Olbrich, M.; Barke, E. (2010): Optimization of Chip Design Processes using Task GraphsInternational Conference on Software Technology and Engineering (ICSTE 2010)
    DOI: 10.1109/ICSTE.2010.5608900
  • Ohlendorf, O.; Olbrich, M.; Barke, E. (2010): Integriertes Einfügen von Repeatern während der PlatzierungedaWorkshop10, VDE-Verlag
    ISBN: 978-3-8007-3252-4
  • Hölldampf, S.; Zaum, D.; Quiring, A.; Neumann, I.; Schmidt, S.; Olbrich, M.; Barke, E. (2010): Beschleunigte Simulation von Mixed-Signal-Schaltungen der Automobilindustrie auf der Grundlage automatisch generierter ModelleAnalog 2-1, VDE-Verlag
    ISBN: 978-3-8007-3224-1
  • Wang, L.; Olbrich, M.; Barke, E.; Büchner, T.; Bühler, M. (2009): Fast Dynamic Power Estimation Considering Glitch FilteringIEEE International SOC Conference (SOCC 2009), (361-364)
    DOI: 10.1109/SOCCON.2009.5398019
  • Harizi, H.; Fischer, H.; Olbrich, M.; Barke, E. (2009): Efficient and Fast Analysis of Power Distribution NetworksIEEE Symposium on Industrial Electronics & Applications (IEEE ISIEA 2009), (425-430)
    DOI: 10.1109/ISIEA.2009.5356442
  • Harizi, H.; Barke, E. (2009): Chip-Level Analysis of Power Distribution NetworksIEEE Regional Symposium on Micro and Nano Electronics (IEEE-RSM2009), (440-446)
  • Harizi, H.; Olbrich, M.; Barke, E. (2009): Modeling and Simulation Techniques for Voltage Drop due to Multiple Input Switching TransitionsInternational Conference on Computer and Electrical Engineering (ICCEE 2009), (546-550)
    DOI: 10.1109/ICCEE.2009.242
  • Zaum, D.; Hoelldampf, S.; Neumann, I.; Schmidt, S.; Olbrich, M.; Barke, E. (2009): The Praise Approach For Accelerated Transient Analysis Applied To Wire ModelsInternational Behavioral Modeling and Simulation Conference (BMAS)
    DOI: 10.1109/BMAS.2009.5338876
  • Jambor, T.; Zaum, D.; Olbrich, M.; Rottke, A. (2009): Combating Skill Shortage in Electrical Engineering: An Action-Oriented Teaching Unit on MicroelectronicsEngineering Education and Educational Technologies, Engineering Education and Educational Technologies(II)
  • Hinrichs, H.; Olbrich, M.; Barke, E. (2009): An Approach for Analyzing and Evaluating Semiconductor Design ProjectsInternational Conference on Systems Engineering and Engineering Management (ICSEEM'09)
  • Hinrichs, H.; Hassine, A..; Barke, E. (2009): Adrenalin - Simulating Chip Design ProcessesUniversity Booth at DATE '09
  • Herzer, S.; Kulkarni, S.; Jankowski, M.; Neidhardt, J.; Wicht, B. (2009): Capacitive-coupled current sensing and Auto-ranging slope compensation for current mode SMPS with wide supply and frequency range2009 Proceedings of ESSCIRC
    DOI: 00 10.1109/ESSCIRC.2009.5326034
  • Hassine, A.; Barke, E. (2008): On Modeling and Simulating Chip Design Processes: The RS ModelIEEE International Engineering Management Conference - Europe, (81-85)
  • Hassine, A.; Barke, E. (2008): Towards Simulation of Chip Design Processes: The Request Service ModelIASTED International Conference on Modelling and Simulation, Quebec, Canada, (193-198)
  • Jambor, T.; Zaum, D.; Olbrich, M.; Barke, E. (2008): A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing AnglesIEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, (54-58)
  • Freisfeld, M.; Olbrich, M.; Barke, E. (2008): Circuit Simulations with Uncertainties using Affine Arithmetic and Piecewise Affine StatemodelsProceedings of International Conference on Solid-State and Integrated-Circuit Technology, IEEE Press
    ISBN: 978-1-4244-2186-2
  • Freisfeld, M.; Olbrich, M.; Pfost, M.; Barke, E. (2008): Verlässliche Modellierung integrierter analoger Schaltungen durch stückweise affine Abbildungen10. GMM/ITG-Fachtagung Analog 2-1, (56), VDE/VDI-Gesellschaft, VDE Verlag GmbH
  • Panitz, P.; Olbrich, M.; Barke, E.; Buehler, M.; Koehl, J. (2008): Considering Possible Opens in Wire Delay Calculation for Non-tree TopologiesACM Great Lakes Symposium on VLSI Proceedings, ACM Great Lakes Symposium on VLSI Proceedings, Association for Computing Machinery, (17-22)
    ISBN: 978-1-59593-999-9
  • Olbrich, M.; Barke, E. (2008): Distribution Arithmetic for Stochastical AnalysisProceedings of the ASP-DAC 2-1, (537-542)
  • Grabowski, D.; Olbrich, M.; Barke, E. (2008): AC-Analyse analoger Schaltungen mit affiner ArithmetikAnalog 2-1, Entwicklung von Analogschaltungen mit CAE-Methoden, GMM/ITG, VDE (63-68)
    ISBN: 978-3-8007-3083-4
  • Grabowski, D.; Olbrich, M.; Barke, E. (2008): Analog Circuit Simulation Using Range ArithmeticsProceedings of the ASP-DAC 2-1, (762-767)
    ISBN: 978-1-4244-1921-0
  • P. Panitz, M. Olbrich, E. Barke, M. Bühler, J. Koehl (2008): Redundanz in Repeaternetzwerken auf ULSI-Chips zur Erhöhung der funktionalen und parametrischen Ausbeute2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", VDE Verlag (8)
    ISBN: 978-3-8007-3119-0
  • Hinrichs, H.; Barke, E. (2008): Applying Performance Management on Semiconductor Design ProcessesIEEE International Conference on Industrial Engineering and Engineering Management, 2008. IEEM 2008., (278 - 281)
  • Hölldampf, S.; Zaum, D.; Neumann, I.; Schmidt, S.; Olbrich, M.; Barke, E. (2008): Methodologies for high-level modelling and evaluation in the automotive domainForum on Specification, Verification and Design Languages, 2008 (FDL 2008)
  • Zaum, D.; Olbrich, M.; Barke, E. (2008): Automatic data extraction: A prerequisite for productivity measurementEngineering Management Conference, 2008 (IEMC Europe 2008)
  • Grabowski, D.; Olbrich, M.; Barke, E. (2008): Simulation analoger Schaltungen mit affiner Arithmetik2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", VDE Verlag
  • Wendt, M.; Thoma, L.; Wicht, B.; Schmitt-Landsiedel, D.; (2008): A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching DelayIEEE Journal of Solid-State Circuits ( Volume: 43 , Issue: 7 , July 2008 )
    DOI: 10.1109/JSSC.2008.923734
  • Harizi, H.; Häußler, R.; Olbrich, M.; Barke, E. (2007): Efficient modeling techniques for dynamic voltage drop analysisProceedings of the 44th annual Design Automation Conference (DAC) 2-1, (706-711)
    ISBN: 978-1-59593-627-1
  • Wendt, M.; Thoma, L.; Wicht, B.; Schmitt-Landsiedel, D. (2007): A configurable High-Side/ low-Side Driver
    DOI: 10.1109/ESSCIRC.2007.4430292
  • Panitz, P.; Olbrich, M.; Barke, E.; Koehl, J. (2007): Robust Wiring Networks for DfY Considering Timing ConstraintsGreat Lakes Symposium on VLSI 2-1, ACM, New York (43-48)
    ISBN: 9781595936059
  • Freisfeld, M.; Olbrich, M.; Grimm, C.; Barke, E. (2007): Verwendung von Gebietsarithmetiken zum Entwurf robuster Schaltungen und Systeme1.GMM/GI/GI-Fachtagung Zuverlaessigkeit und Entwurf, VDE Verlag, Berlin (131-136)
    ISBN: 9783800730230
  • Panitz, P.; Quiring, A.; Mueller, H.-C.; Olbrich, M.; Barke, E.; Koehl, J. (2007): Erhoehung der Ausbeute durch robuste Verdrahtungsnetzwerke1.GMM/GI/GI-Fachtagung Zuverlaessigkeit und Entwurf, VDE Verlag GmbH - Berlin, Offenbach (117-123)
    ISBN: 9783800730230
  • Zhang, M.; Olbrich, M.; Seider, D.; Frerichs, M.; Kinzelbach, H.; Barke, E. (2007): Ein Verfahren zur Analyse der Prozessschwankungen für nichtlineare Schaltungen mit nicht-Gauss-verteilten Parametern1.GMM/GI/ITG-Fachtagung Zuverlaessigkeit und Entwurf, VDE VERLAG GMBH, Berlin (25-30)
    ISBN: 9783800730230
  • Jambor, T.; Olbrich, M.; Barke, E. (2007): Corner-Stitching-Datenstruktur für beliebige LayoutstrukturenEDA Workshop 2-1, VDE (41 - 46)
    ISBN: 9783800730384
  • Weinkopf, J. T.; Harbich, K.; Barke, E. (2007): Incremental Fault Emulation17th International Conference on Field Programmable Logic and Applications, Delft University of Technology, Delft (542-545)
    ISBN: 1424410606
  • Häusler, S.; Poppen, F.; Preis, S.; Hausmann, K.; Nebel, W.; Hahn, A.; Leppelt, P.; Hassine, A.; Barke, E.) (2007): Modellierung von Komplexität und Qualität als Faktoren von Produktivität in Design-Flows für integrierte Schaltungen
  • Hinrichs, N.; Leppelt, P.; Barke, E. (2007): Building up a Performance Measurement System to Determine Productivity Metrics of Semiconductor Design ProjectsIEEE International Engineering Management Conference (IEMC), Austin Texas, IEEE, IEEE (CD-ROM Proceedings)
    ISBN: 978-1-4244-2146-6
  • Grabowski, D.; Olbrich, M.; Grimm, C.; Barke, E. (2007): Range Arithmetics to Speed up Reachability Analysis of Analog SystemsFDL 2-1, (CD-ROM)
  • Zhang, M.; Olbrich, M.; Seider, D.; Frerichs, M.; Kinzelbach, H.; Barke, E. (2007): CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear FunctionsDesign, Automation and Test in Europe (DATE2007), IEEE Catalog Number 07EX1635 (243 - 248)
    ISBN: 9783981080124
  • Ohlendorf, O.; Olbrich, M.; Barke, E. (2007): Timing-Driven-3D-Platzierung mit einem kräftebasierten Ansatz1.GMM/GI/GI-Fachtagung Zuverlaessigkeit und Entwurf, VDE Verlag GmbH, Berlin (187-188)
    ISBN: 9783800730230
  • R. Klausen, L. Hedrich, E. Barke (2006): Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen9. Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), saxOprint, Dresden (122-131)
    ISBN: 3981028716
  • D. Grabowski, C. Grimm, E. Barke (2006): Semi-Symbolic Modeling and Simulation of Circuits and SystemsIEEE International Symposium on Circuits and Systems (ISCAS 2006), IEEE, Kos (CD-ROM)
    ISBN: 0-7803-9390-2
  • D. Grabowski, C. Grimm, E. Barke (2006): Ein Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen9. Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Fraunhofer IIS (181-190)
    ISBN: 3-9810287-1-6
  • Leppelt, P.; Hassine, A.; Barke, E. (2006): An Approach to Make Semiconductor Design Projects Comparable7th Asia Pacific Industrial Engineering and Management Systems Conference (APIEMS 2006), Asian Institute of Technology (CD-ROM)
    ISBN: 974-8257-26-6
  • Hassine, A.; Olbrich, M.; Barke, E. (2006): Computer Aided HRM for the Semiconductor Industry: Computer Aided HRM for the Semiconductor Industry: Limits and Perspectives7th Asia Pacific Industrial Engineering and Management Systems Conference (APIEMS 2006), (CD_ROM)
  • Ohlendorf, O.; Olbrich, M.; Barke, E. (2006): Global Routing for Force Directed PlacementProceedings 10th IEEE Workshop on Signal Propagation on Interconnects (SPI06), IEEE (25-29)
    ISBN: 1424404541
  • Jambor, T.; Olbrich, M.; Barke, E.; Köhne, J. (2006): RL-Analysis of Meander Shaped Adjustment Modules10th IEEE Workshop on Signal Propagation on Interconnects
  • Weinkopf, J. T.; Harbich, K.; Barke, E. (2006): PARSIFAL: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models16th International Conference on Field Programmable Logic and Applications, Publidisa, Madrid (241-246)
    ISBN: 142440312X
  • Zhang, M.; Olbrich, M.; Kinzelbach, H.; Seider, D.; Barke, E. (2006): A Fast and Accurate Monte Carlo Method for Interconnect VariationICICDT 2006 Proceedings, (207-210)
  • Panitz, P.; M. Olbrich, E. Barke, J. Koehl (2006): Global Loops on ULSI Routing for DfYICICDT 2006 Proceedings, Padova, IEEE (179-182)
    ISBN: 1424400988
  • Amir Hassine, Erich Barke (2005): An Automated Approach to Measure Design Productivity Based on Quality Metrics in a Semiconductor Design ProcessAsia Pacific Industrial Engineering and Management Society Conference, Manila (Philippines), (CD-ROM)
  • Oehmen, J.; Olbrich, M.; Barke, E. (2005): Modeling Substrate Currents in Smart Power ICsInt. Symp. on Power Semiconductor Devices and ICs 2005 (ISPSD05), IEEE (127-130)
    ISBN: 0-7803-8889-5
  • Joerg Oehmen, Lars Hedrich, Markus Olbrich, Erich Barke (2005): A Methodology for Modeling Lateral Parasitic Transistors in Smart Power ICs 2005 IEEE International Behavioral Modeling and Simulation Conference, IEEE (19-24)
    ISBN: 078039352x
  • Amir Hassine, Erich Barke (2005): Measure your Design Value to Improve ItIEEE International Engineering Management Conference. St. John's, Newfoundland, Kanada CD-ROM, Proceedings of 2005 IEEE International Engineering Management Conference, Newfoundland & Labrador, Canada.
    ISBN: 0780391403
  • Philipp Panitz, Markus Olbrich, Erich Barke (2005): Detailed Routing With Integrated Static Timing Analysis Applying Simulated AnnealingProceedings of the IEEE Northeastern Workshop on Circuits and Systems, IEEE (387-390)
    ISBN: 0780389344
  • D. Grabowski, D. Platte, L. Hedrich, E. Barke (2005): Time Constrained Verification of Analog Circuits using Model-Checking AlgorithmsENTCS, ETAPS 2005
  • Schreiner, L.; Olbrich, M.; Barke, E.; Meyer zu Bexten, V. (2005): Routing of Analog Busses with Parasitic SymmetryInternational Symposium on Physical Design, ACM Press, New York (14-19)
    ISBN: 1-59593-021-3
  • Jambor, T.; Schreiner, L.; Olbrich, M.; Barke, E. (2005): Net order optimization in analog net bundlesMicrotechnologies for New Millenium 2005
  • D. Platte, D. Grabowski, L. Hedrich, E. Barke (2005): Verifikation von Zeitbedingungen analoger Schaltungen durch Model-Checking-VerfahrenAnalog 2005: 8. ITG/GMM-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (159-164)
  • Volodymyr Burkhay, Sebastian Breutmann, Lars Hedrich, Erich Barke (2005): Symbolische Analyse nichtlinearer analoger Schaltungen mit Hilfe Branch-and-Bound-optimierter VereinfachungANALOG'05 (8. GMM/ITG-Diskussionssitzung), VDE, Berlin (253-258)
    ISBN: ISBN 3800728818
  • Schreiner, L.; Olbrich, M.; Barke, E.; Meyer zu Bexten, V. (2005): PARSY: PARasitenSYmmetrische Verdrahtung für analoge Busse mit ModulgeneratorenANALOG'05 (8. GMM/ITG-Diskussionssitzung), VDE Verlag GmbH, Berlin, Offenbach (283-288)
    ISBN: 3-8007-2881-8
  • R. Klausen, L. Hedrich, E. Barke (2005): Äquivalenz-Vergleich nichtlinearer analoger MIMO-Systeme mit automatischer SchrittweitensteuerungAnalog 2005: 8. ITG/GMM-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, VDE-Verlag, Berlin (183-188)
    ISBN: 3800728818
  • Olbrich, M.; Barke, E. (2004): Placement Using a Localization Probability Model (LPM)Proceedings Design, Automation and Test in Europe (DATE2004), IEEE Computer Society, Los Alamitos (1412-1413)
    ISBN: 0769520855
  • Näthke, L.; Burkhay, V.; Hedrich, L.; Barke, E. (2004): Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits based on Nonlinear Symbolic TechniquesProceedings Design, Automation and Test in Europe (DATE2004), IEEE Computer Society, Los Alamitos (442-447)
    ISBN: 0769520855
  • Kaya, I.; Salewski, S.; Olbrich, M.; Barke, E. (2004): Wirelength Reduction Using 3-D Physical DesignPATMOS 2-1, (453-462)
  • Wicht, B.; Nirschl, T.; Schmitt-Landsiedel, D. (2004): Yield and speed optimization of a latch-type voltage sense amplifierIEEE Journal of Solid-State Circuits ( Volume: 39 , Issue: 7 , July 2004 )
    DOI: 10.1109/JSSC.2004.829399
  • Lemke, A.; Hedrich, L.; Barke, E. (2003): Dimensionierung analoger Schaltungen mit formalen Methoden7. ITG/GMM-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, VDE-Verlag, Berlin (135-140)
    ISBN: 3-8007-2778-1
  • Hermann, A.; Olbrich, M.; Barke, E. (2003): Substrate Modeling and Noise Reduction in Mixed-Signal CircuitsProc. of IFIP VLSI SoC, Darmstadt (13-18)
    ISBN: 3901882170
  • Hermann, A.; Olbrich, M.; Barke, E. (2003): Placing Substrate Contacts into Mixed-Signal Circuits Controlling Circuit PerformanceProc. Of 25th IEEE Custom Integrated Circuits Conference, (373-376)
  • Kaya, I.; Olbrich, M.; Barke, E. (2003): 3-D Placement Considering Vertical InterconnectsProceedings of the IEEE International SOC Conference, (257-258)
    ISBN: 0780381823
  • Salewski, S.; Olbrich, M.; Barke, E. (2003): LIFT: Ein Multi-Layer IC Floorplanning Tool11. E.I.S.-Workshop: Entwurf Integrierter Schaltungen und Systeme, VDE Verlag GmbH (157-162)
    ISBN: 3800727609
  • Malonnek, C.; Olbrich, M.; Barke, E. (2003): Ein neues Platzierungsverfahren für einen leitbahnzentrierten DesignflowE.I.S.-Workshop, VDE VERLAG GmbH (151-156)
    ISBN: 3800727609
  • Wicht, B.; Nirschl, T.; Schmitt-Landsiedel, D. (2003): A yield-optimized latch-type SRAM sense amplifierESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)
    DOI: 10.1109/ESSCIRC.2003.1257159
  • Wicht, B.; Larguier, J.; Schmitt-Landsiedel, D. (2003): A 1.5V 1.7ns 4k /spl times/ 32 SRAM with a fully-differential auto-power-down current sense amplifier2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
    DOI: 10.1109/ISSCC.2003.1234387
  • Abke, J.; Barke, E. (2002): A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAsD.A.TE 2002: 5th Design Automation and Test in Europe, IEEE Computer Society (1085)
    ISBN: 0769514715
  • Malonnek, C.; Olbrich, M.; Barke, E. (2002): A New Placement Algorithm for an Interconnect Centric Design FlowASIC/SOC 2-1, IEEE Press (416-420)
    ISBN: 0780374940
  • Lemke, A.; Hedrich, L.; Barke, E. (2002): Analog Circuit Sizing Based on Formal Methods Using Affine ArithmeticICCAD 2-1, IEEE Computer Society (486-489)
    ISBN: ISBN 0780376072
  • Hartong, W.; Hedrich, L.; Barke, E. (2002): On Discret Modeling and Model Checking for Nonlinear Analog SystemsCAV 2002: Conference on Computer-Aided Verification, Springer Verlag, Berlin
  • Näthke, L.; Hedrich, L.; Barke, E. (2002): Betrachtungen zur Simulationsgeschwindigkeit von Verhaltensmodellen nichtlinearer integrierter AnalogschaltungenAnalog 2-1, (107-112)
  • Hartong, W.; Hedrich, L.; Barke, E. (2002): Model Checking Algorithms for Analog VerificationDAC 2002
  • Hartong, W.; Hedrich, L.; Barke, E. (2002): An Approach to Model Checking for Nonlinear Analog SystemsDate 2-1, IEEE Computer Society, Los Alamitos (1080-1080)
    ISBN: 0769514715
  • Salewski, S.; Barke, E. (2002): An Upper Bound for 3D Slicing FloorplansProceedings of 7th ASPDAC and 15th Int'l Conf. on VLSI Design (2002), IEEE Computer Society Press, Los Alamitos (567-572)
    ISBN: 0769514413
  • Popp, R.; Oehmen, J.; Hedrich, L.; Barke, E. (2002): "Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits"DATE2002: 5th Design Automation and Test in Europe, IEEE Computer Soc., Los Alamitos, CA (274-278)
    ISBN: 0769514715
  • Kulaczewski, B.; Zimmermann, S.; Barke, E.; Pirsch, P. (2001): CHIPDESIGN - A Novel Project-oriented Microelectronics Course2001 International Conference on Microelectronic Systems Education (MSE 2001), IEEE Computer Society, Los Alamitos, USA (71-72)
    ISBN: 0769511562
  • Näthke, L.; Popp, R.; Hedrich, L.; Barke, E. (2001): Automatic Analog Behavioral Model GenerationUniversity Booth DATE2001: 4th Design Automation and Test in Europe
  • Olbrich, M.; Rein, A.; Barke, E. (2001): An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated CircuitsDATE2001: 4th Design Automation and Test in Europe, (807)
  • Küter, J.; Barke, E. (2001): Architecture Driven PartitioningDATE2001: 4th Design Automation and Test in Europe, (479-485)
  • Hermann, A.; Gärtner, R.; Schlöffel, J.; Barke, E. (2001): Extraktion und Simulation parasitärer Substrateffekte an einer Mixed-Signal CMOS-Schaltung10. E.I.S.-Workshop: Entwurf integrierter Schaltungen (8. ITG-Fachtagung), (75-80)
  • Lienig, J.; Jerke, P. Decker, P.;. Gerbershagen, M.; Stürmer, A.; Adler, T.; Schreiner, L.;Barke, E. (2001): Stromabhängige Verdrahtung von Analogschaltungen10. E.I.S.-Workshop: Entwurf integrierter Schaltungen (8. ITG-Fachtagung), (167-170)
  • Harbich, K.; Bringmann, O.; Barke, E. (2001): PuMA++: A Fully Automatic Path from Specification to Multi-FPGA-PrototypeFPGA 01: International Conference on Field Programmable Gate Arrays
  • Olbrich, M.; Popp, R.; Näthke, L.; Hedrich, L.; Barke, E. (2001): A Combined Structural and Symbolic Method for Automatic Behavioral Modeling of Nonlinear Analog CircuitsProceedings of the 15th European Conference on Circuit Theory and Design (ECCTD 01), Helsinki University of Technology, Espoo, Finnland (II-229-232)
    ISBN: 9512255731
  • Armbruster, H.; Frerichs, M.; Hufeld, K.; Olbrich, M. (2001): Ein integrierter parallelisierter Design-Flow zur selektiven und hochgenauen Extraktion parasitärer Elemente der Leitbahnen integrierter Schaltungen10. E.I.S.-Workshop: Entwurf integrierter Schaltungen (8. ITG-Fachtagung), VDE Verlag, Berlin, Offenbach (149-154)
    ISBN: 3800726084
  • Abke, J.; Barke, E. (2001): A New Placement Method for Direct Mapping into LUT-Based FPGAsFPL2001: 11th Conference on Field-Programmable Logic and Applications, (27-36)
  • Wicht, B.; Paul, S.; Schmitt-Landsiedel, D. (2001): Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiersIEEE Journal of Solid-State Circuits ( Volume: 36 , Issue: 11 , Nov 2001 )
    DOI: 10.1109/4.962297
  • Wicht, B.; Schmitt-Landsiedel, D.; Paul, S. (2001): A simple low voltage current sense amplifier with switchable input transistorProceedings of the 27th European Solid-State Circuits Conference
  • Nirschl, T.; Wicht, B.; Schmitt-Landsiedel, D. (2001): High Speed, Low Power Design Rules for SRAMPrecharge and Self-timing under TechnologyVariations
  • Wicht, B.; Martiny, I.; Schmitt-Landsiedel, D.; Paul, S.; Sanders, A. (2001): Speeding up CMOS cameras and optical receivers by improved column multiplexerOptoelectronic Integrated Circuits and Packaging V
  • Wicht, B.; Schmitt-Landsiedel, D.; Paul, S.; Sanders, A. (2001): SRAM current-sense amplifier with fully-compensated bit line multiplexer2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)
    DOI: 10.1109/ISSCC.2001.912591
  • Wicht, B.; Paul, S.; Schmitt-Landsiedel, D. (2001): MEMORY PAPERS-Analysis and Compensation of the Bitline Multiplexer in SRAM Current Sense AmplifiersIEEE Journal of Solid State Circuits-Institute of Electrical and Electronics Engineers
  • Popp, R.; Barke, E. (2000): Symbolic Analysis of Nonlinear Analog Circuits by Simplification of Nested ExpressionsSMACD 2000: Proc. 7th Int. Workshop on Symbolic Methods and Applications in Circuit Design, (151-154)
  • Hermann, A.; Silvant, M.; Schlöffel, J.; Barke, E. (2000): PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-CircuitsPATMOS 2000: 10th International Workshop, (306-315)
  • Ringe, M.; Lindenkreuz, T.; Barke, E. (2000): Static Timing Analysis Taking Crosstalking into AccountDATE 2000: 3th Design Automation and Test in Europe, (451-455)
  • Adler, L.; Barke, E. (2000): Single Step Current Driven Routing of Multiterminal Signal Nets for Analog ApplicationsDATE 2000: 3th Design Automation and Test in Europe, (446-450)
  • Harbich, K.; Abke, J.; Barke, E. (2000): An Optimised Partitioning and Mapping Environment for Rapid Prototyping of Structural RT-level Circuit DescriptionsDATE 00: 3rd Design Automation and Test in Europe, University Booth
  • Adler, T.; Brocke, H.; Hedrich, L.; Barke, E. (2000): A Current Driven Routing and Verification Methodology for Analog ApplicationsDAC 2000: 37th Design Automation Conference, (385-389)
  • Brocke, H.; Hedrich, L.; Klausen, R.; Barke, E. (2000): Current Density Calculation of Integrated Circuit InterconnectMICRO.tec 2000 Proceedings Volume 2, VDE Verlag, Berlin (77-81)
    ISBN: 3800725797
  • Abke, J.; Barke, E. (2000): CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAsFPL2000: 10th Conference on Field-Programmable Logic and Applications, (191-200)
  • Martiny, I.; Leuner, R.; Wicht, B. (2000): Cross-talk reduction and efficiency of integrated photodiodes shown by an integrated edge detectorOptoelectronic Integrated Circuits IV
  • W. Hartong, L. Hedrich, E. Barke (1999): Ein Ansatz zur formalen Verifikation nichtlinearer statischer Analogschaltungen mit ParametertoleranzenAnalog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (93-94)
  • Olbrich, M.; Rein, A.; Barke, E. (1999): Ein neuer hierarchischer Klassifizierungsalgorithmus zur strukturellen Analyse integrierter SchaltungenAnalog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (77+78)
  • A. Lemke, W. Hartong, E. Barke (1999): Dimensionierung analoger Schaltungen unter Verwendung intervallarithmetischer VerfahrenAnalog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (87-88)
  • F. Shaikh-Brocke, L. Hedrich, T. Adler, E. Barke, M. Laage, A. Stürmer, C. Rödel (1999): Berechnung der Stromdichten des Leitbahnsystems integrierter SchaltungenAnalog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (52-53)
  • M. Klemme, E. Barke (1999): An Extended Bipolar Transistor Model For Substrate Crosstalk AnalysisSSCS 99: IEEE Custom Integrated Circuits Conference, (579-582)
  • M. Klemme, E. Barke (1999): Modellierung von Übersprechen durch das Substrat für die Schaltungssimulation von integrierten Mixed-Signal-SchaltungenAnalog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (66+67)
  • S. Zimmermann, E. Barke (1999): Benchmarking von RLC-NetzwerkreduktionsverfahrenAnalog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (145-146)
  • L. Näthke, R. Popp, L. Hedrich, E. Barke (1999): Using Term Ordering to Improve Symbolic Behavioral Model Generation of Nonlinear Analog CircuitsECCTD99: European Conference on Circuit Theory and Design, (74-77)
  • C. Malonnek, E. Barke (1999): Entwurf eines Testchips zur Messung parasitärer EffekteAnalog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (68+69)
  • M. Klemme, J. Schlöffel, E. Barke (1999): Modélisation de couplage électromagnétique par le substrat pour la simulation des circuits intégrésFTFC99: 2ème Journées Francophones d'études Faible Tension Faible Consommation, Recueil des Communications, (S.119-125)
  • K. Harbich, J. Stohmann, L. Schwoerer, E. Barke (1999): A Case Study: Logic Emulation - Pitfalls and SolutionsRSP 99: 10th IEEE Workshop on Rapid System Prototyping, (160-163)
  • J. Abke, E. Barke, M. Heeke, D. Kannemacher (1999): RIG: Targeting Designs with Embedded Memories to ASIC and FPGA TechnologiesInternational Workshop on IP Based Synthesis and System Design, (237-240)
  • J. Abke, J. Stohmann, E. Barke (1999): A Universal Module Generator for LUT-Based FPGAs10th IEEE Workshop on Rapid System Prototyping, (230-235)
  • L. Hedrich, E. Barke (1998): A Formal Approach to Verification of Linear Analog Circuits with Parameter TolerancesDATE 98: Design, Automation and Test in Europe
  • M. Klemme, E. Barke (1998): Accurate Junction Capacitance Modelling for Substrate Crosstalk CalculationPATMOS 1998: 8th International Workshop, (297-306)
  • Stohmann, J.; Harbich, K.; Olbrich, M.; Barke, E. (1998): An Optimized Design Flow for Fast FPGA-Based Rapid PrototypingFPL 98: 8th Int. Workshop on Field Programmable Logic and Applications, (79-88)
  • R. Sedaghat, E. Barke (1998): Real Time Fault Injection Using Logic EmulatorASP-DAC 98: Asia and South Pasific Design Automation Conference 1998
  • K. Harbich, H. Hoffmann, E. Barke (1998): A New Hierachical Graph Model for Multiple FPGA PartitioningWDTA 98: IEEE Workshop on Design, Test and Application, (101-104)
  • R. Popp, W. Hartong, L. Hedrich, E. Barke (1998): Error Estimation on Symbolic Behavioral Models of Nonlinear Analog CircuitsSMACD 1998: 5th International Conference on Symbolic Methods and Applications to Circuits Design
  • M. Klemme, E. Barke (1997): Modellierung und Simulation von Substratkoppelungen in bipolaren integrierten SchaltungenMikroelektronik 97, (61-66)
  • D. Behrens, R. Tolkiehn, E. Barke (1997): Design Driven PartitioningASP-DAC 97: 2nd Asia and South Pacific Design Automation Conference
  • J. Stohmann, E. Barke (1997): An Universal Booth-Multiplier Generator for SRAM-Based FPGAsFPGA 97: 5th International Symposium on Field-Programmable Gate Arrays
  • J. Stohmann, Barke E.; (1997): A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAsICCD 97: International Conference on Computer Design, (489-495)
  • R. Sedaghat-Maman, E. Barke (1997): A New Approach to Fault EmulationRSP 97: 8th IEEE International Conference on Rapid Systems Prototyping, (173-179)
  • M. Ringe, T. Lindenkreuz, E. Barke (1997): Das allgemeine Problem der falscher Pfade: Ein Überblick4. SICAN Herbsttagung, (227-232)
  • R. Kattner, F. Scherber, L. Beste, C. Müller-Schloer, E. Barke (1996): Speeding Up Parallel Layout Verification by Simulation-Based Task SchedulingESS 96: 8th European Simulation Symposium
  • D. Behrens, K. Harbich, E. Barke (1996): Hierarchical PartitioningICCAD 96: Int. Conference on Comuter Aided Design, (470-477)
  • D. Behrens, K. Harbich, E. Barke (1996): Circuit Partitioning Using High-Level Design InformationIDPT 96: 2nd World Conference on Integrated Design & Process Technology, (256-266)
  • J. Stohmann, E. Barke (1996): An Universal CLA Adder Generator for SRAM-Based FPGAsFPL 96: 6th Int. Workshop on Field-Programmable Logic and Applications, (44-54)
  • F. Scherber, E. Barke, W. Meier (1996): PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit ExtractorED&TC 96: European Design and Test Conference, (357-361)
  • C. Borchers, L. Hedrich, E. Barke (1996): Equation-Based Behavioral Model Generation for Nonlinear Analog CircuitsDAC 96: 33rd Design Automation Conference, (236-239)
  • L. Hedrich, E. Barke (1995): A Formal Approach to Nonlinear Analog Circuit VerificationICCAD 95: Int. Conference on Computer Aided Design, (123-127)
  • L. Hedrich, E. Barke (1995): Ein Verfahren zur Verifikation nichtlinearer analoger Schaltungen2. ITG-Diskussionssitzung Neue Anwendungen theoretischer Konzepte in der Elektrotechnik, (145-147)
  • C. Borchers, S. Lucke, E. Barke (1994): Integration der Monte-Carlo-Analyse in eine Schaltungsumgebung3. GI/ITG/GME-Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, (96-104)
  • C. Borchers, J. Wagner, E. Barke (1993): Verhaltensmodell und Simulation eines Radio-Koinzidenzdemodulator2. GME/ITG Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, (114-118)
  • C. Borchers, B. Ludwig, E. Barke (1993): Reduktion parasitärer RC-Netzwerke in höchstintegrierten Schaltungen6. E.I.S.- Workshop, (361-368)

Journalbeiträge

  • Seidel, A.; Wicht, B. (2018): Drei Stufen geben SicherheitDesign & Elektronik : Know-How für Entwickler
    ISSN: 0933-8667
  • Zivkovic, C.; C. Grimm, C.; Olbrich, M.; Scharf, O.; Barke, E. (2018): Hierarchical Verification of AMS Systems With Affine Arithmetic Decision DiagramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1–12 Weitere Informationen
    DOI: 10.1109/TCAD.2018.2864238
  • Barke, M.; Kaergel, M.; Olbrich, M.; Schlichtmann, U. (2014): Robustness measurement of integrated circuits and its adaptation to aging effectsMicroelectronics Reliability (Volume 54, Issue 6-7)
    DOI: 10.1016/j.microrel.2014.01.012
  • Panitz, P.; Olbrich, M.; Barke, E.; Buehler, M.; Koehl, J. (2008): Design of Robust Signal and Clock NetworksProceedings in Applied Mathematics and Mechanics, Proceedings in Applied Mathematics and Mechanics(Volume 7, Issue 1), GAMM, Wiley InterScience (2)
    DOI: 10.1002/pamm.200700468
  • Oehmen, J.; Olbrich, M.; Hedrich, L.; Barke, E. (2006): Modeling Lateral Parasitic Transistors in Smart Power ICsIEEE Transactions on Device and Materials Reliability, 6(3), IEEE (408-420)
    DOI: 10.1109/TDMR.2006.881506
    ISBN: 15304388
  • E. Barke (1996): Bei Electronic Design Automation bleibt der Weg das ZielF&M, 104(6)

Dissertationen

  • Olbrich, M. (2005): Platzierung in integrierten Schaltungen mit AufenthaltswahrscheinlichkeitenDissertation, Verlag Dr. Hut, München
    ISBN: 3899632761

Sonstiges

  • Gläser, G.; Lee, H.-S. L.; Hennig E.; Olbrich, M.; Barke E. (2016): Automated Refinement of Analog/Mixed-Signal SystemC Models by Non-Functional EffectsUniversity Booth at DATE 2016, Design, Automation & Test in Europe Conference & Exhibition), Dresden, Germany. Weitere Informationen
  • Martiny, I.; Wicht, B. (2000): Integrierter Bildaufnehmer für das Kohärenzradar (Integrated Optical Sensor for the Coherence Radar System)

Buchbeiträge

  • Gläser, G.; Lee, H.-S. L.; Olbrich, M.; Barke, E. (2018): Knowing Your AMS System's Limits: System Acceptance Region Exploration by Using Automated Model Refinement and Accelerated SimulationLanguages, Design Methods, and Tools for Electronic System Design, Springer, pp. 1-14
    DOI: 10.1007/978-3-319-62920-9
    ISBN: 978-3-319-62919-3
  • Knoth, C.; Schlichtmann, U.; Li, B.; Zhang, M.; Olbrich, M.; Acar, E.; Eichler, U.; Haase, J.; Lange, A.; Pronath, M. (2012): Methods of Parameter VariationsProcess Variations and Probabilistic Integrated Circuit Design, S. 91–179, Springer, 2012
    DOI: 10.1007/978-1-4419-6621-6
  • Schupfer, F.; Kärgel, M.; Grimm, C.; Olbrich, M.; Barke, E. (2012): Towards Abstract Analysis Techniques for Range Based System SimulationSystem Specification and Design Languages, Selected Contributions from FDL, Volume 106, pp. 105-122, Springer
    DOI: 10.1007/978-1-4614-1427-8_7
    ISBN: 978-1-4614-1427-8
  • Daniel Platte, D.; Shangjing Jing, S.; Ralf Sommer, E and Erich Barke (2007): Improving Efficiency and Robustness of Analog Behavioral Models Advances in Design and Specification Languages for Embedded Systems Selected Contributions from FDL'06, Sorin A. Huss, Springer Netherlands (53-68)
    ISBN: 978140206147

Bücher

  • Wicht, B.; Wittmann, J.; Seidel, A.; Schindler, A. (2016): High-Voltage Fast-Switching Gate Drivers
    DOI: 10.1007/978-3-319-41670-0_9
  • Wicht, B. (2013): Current Sense Amplifiers for Embedded SRAM in High-Performance System-on-a-Chip Designs
    ISBN: 978-3-642-05557-7
    ISSN: 1437-0387
  • Wicht, B. (2003): Fundamentals of SRAM and Sensing
    DOI: 10.1007/978-3-662-06442-9_2
  • Wicht, B. (2003): Voltage Sense Amplifiers
    DOI: 10.1007/978-3-662-06442-9_3
  • Wicht, B. (2003): Circuit Principles for Current Sensing
    DOI: 10.1007/978-3-662-06442-9_4
  • Wicht, B. (2003): Interaction with the Memory Cell
    DOI: 10.1007/978-3-662-06442-9_6
  • Wicht, B. (2003): Analysis and Compensation of the Bitline Multiplexer
    DOI: 10.1007/978-3-662-06442-9_5
  • Wicht, B. (2003): Implementation Aspects
    DOI: 10.1007/978-3-662-06442-9_7
  • Barke, E.; Soudris, D.; Pirsch, P. (Ed.) (2000): Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation (PATMOS 2000: Proceedings 10th International Workshop)Springer Verlag, Heidelberg