Publikationen des Instituts für Mikroelektronische Systeme


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2017


Webering F, Payá Vayá G, Aditya E, Dürre JC, Blume HC. An Integrated Heated Testbench for Characterizing High Temperature ICs. in ICT.OPEN Proceedings 2017. 2017


Weißbrich M, Payá-Vayá G, Gerlach L, Blume H, Najafi A, García-Ortiz A. FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework. in 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society. 2017. S. 1-8 doi.org/10.1109/PATMOS.2017.8106956


Wielage M, Cholewa F, Riggers C, Pirsch P, Blume H. Parallelization strategies for fast factorized backprojection SAR on embedded multi-core architectures. in 2017 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS). IEEE Computer Society. 2017 doi.org/10.1109/COMCAS.2017.8244770


2016


Arndt OJ, Linde T, Blume H. Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture. in 2015 IEEE Global Conference on Signal and Information Processing (GlobalSIP). IEEE Computer Society. 2016. S. 1402-1406 doi.org/10.1109/GlobalSIP.2015.7418429


Baydakov K, Roskamp S, Wohnrade K, Dürre JC, Blume HC. A Scalable Architecture for Low-Latency Network- Encryption in Low-Power Devices. 2016. Postersitzung präsentiert bei International Conference on Field-Programmable Logic and Applications, . doi.org/10.13140/RG.2.2.21476.78722


Blume HC, Mentzer N. Analyzing the Performance-Hardware Trade-off of ASIP-based Image Feature Extraction. 2016. Tensilica Day 2016, Hannover, Deutschland.


Blume HC. LibARITH - A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor Architectures: D3.43: Individual TTP43 abstract. in LibARITH - A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor Architectures. 2016


Blume HC. Mobile platform for real-time sonification of movements for medical rehabilitation: D3.43: Individual TTP43 abstract. in Mobile platform for real-time sonification of movements for medical rehabilitation. 2016


Dürre J, Payá Vayá G, Blume H. Teaching Digital Logic Circuit Design via Experiment-Based Learning - Print your own Logic Circuit. in Callaos NC, Sanchez B, Lace N, Savoie M, Tremante A, Hrsg., 20th World Multi-Conference on Systemics, Cybernetics and Informatics: Proceedings. Band 1. International Institute of Informatics and Systemics, IIIS. 2016. S. 242-247


Gerlach LK, Nolting S, Blume HC, Payá Vayá G, Stolberg H-J, Reuter C. A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor Architectures: Poster. in LibARITH - A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor Architectures. 2016


Gerlach LK, Payá Vayá G, Blume HC. A Low Latency Multichannel Audio Interface for Low Power SIMD Digital Signal Processors. 2016. Beitrag in ICT.OPEN 2016, Amsterfoort, Niederlande.


Gerlach L, Payá-Vayá G, Blume H. Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. in IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society. 2016. S. 254-259 doi.org/10.1109/SiPS.2016.52


Hesselbarth S, Schewior G, Blume H. Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation. in Cerisier S, Morawiec A, Hrsg., Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing: DASIP . IEEE Computer Society. 2016 doi.org/10.1109/DASIP.2015.7367249


Hesselbarth S, Schewior G, Blume H. FPGA emulation methodology for fast and accurate power estimation of embedded processors. Journal of Systems Architecture. 2016 Dez 24;77:14-25. doi.org/10.1016/j.sysarc.2016.12.008


Hwang TH, Reh J, Effenberg A, Blume H. Real-time gait event detection using a single head-worn inertial measurement unit. in Wilson T, Endemann W, Cycon HL, Hepper D, Flores-Arias JM, Hrsg., 2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin). IEEE Computer Society. 2016. S. 28-32 doi.org/10.1109/ICCE-Berlin.2016.7684709


Maschhoff P, Heene S, Lavrentieva A, Hentrop T, Leibold C, Wahalla MN et al. An intelligent bioreactor system for the cultivation of a bioartificial vascular graft. Engineering in life sciences. 2016 Dez 6;17(5):567-578. doi.org/10.1002/elsc.201600138


Nolting S, Payá-Vayá G, Giesemann F, Blume H, Niemann S, Müeller-Schloer C. Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture. in 2016 IEEE 30th International Parallel and Distributed Processing Symposium: Program & Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. S. 172-180 doi.org/10.1109/IPDPSW.2016.158


Pfefferkorn D, Blume HC. Mobile Platform for Real-time Sonification of Movements for Medical Rehabilitation: Poster. in Mobile Platform for Real-time Sonification of Movements for Medical Rehabilitation. 2016


Rath J, Dürre JC, Blume HC. A General Purpose FPGA-Accelerator with Standard USB 3.0 Interface. 2016. Postersitzung präsentiert bei International Conference on Field-Programmable Logic and Applications, .


Schmädecke I, Blume H. Hardware architectures for music classification. in Music Data Analysis: Foundations and Applications. CRC Press. 2016. S. 641-663. (Computer Science and Data Analysis Series). doi.org/10.1201/9781315370996


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