Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

verfasst von

Sven Gesper, Moritz Weissbrich, Tobias Stuckenberg, Pekka Jaaskelainen, Holger Blume, Guillermo Paya-Vaya

Abstract

Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5× higher performance and 2.4× higher computational energy efficiency at a 1.6× larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Externe Organisation(en)

Tampere University

Typ

Artikel

Journal

International Journal of Parallel Programming

Band

49

Seiten

541-569

Anzahl der Seiten

29

ISSN

0885-7458

Publikationsdatum

08.2021

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Software, Theoretische Informatik, Information systems

Ziele für nachhaltige Entwicklung

SDG 7 – Erschwingliche und saubere Energie

Elektronische Version(en)

https://doi.org/10.1007/s10766-020-00686-8 (Zugang: Offen)