Prof. em. Dr.-Ing. Peter Pirsch

Prof. em. Dr.-Ing. Peter Pirsch
Adresse
Appelstraße 4
30167 Hannover
Gebäude
Raum
304
Adresse
Appelstraße 4
30167 Hannover
Gebäude
Raum
304
  • Publikationsliste

    Konferenzbeiträge

    • Jachalsky, J.; Kulaczewski, B.; Pirsch, P. (2002): Project Management and Verification - The Key Problems of Student Chip Design CoursesProceedings of the 32nd ASEE/IEEE Frontiers in Education Conference (FIE 2002), IEEE Press, Piscataway, NJ (CD-ROM)
      ISBN: 0780374452
    • Kropp, H.; Reuter, C.; Wiege, M.; Pirsch, P. (1998): Emulation von Bildverarbeitungsverfahren am Beispiel der Diskreten Cosinus TransformationITG Fachtagung Mikroelektronik für die Informationsverarbeitung, ITG Fachbericht 147 (71-76)
    • Kulaczewski, B.; Zimmermann, S.; Barke, E.; Pirsch, P. (2001): CHIPDESIGN - A Novel Project-oriented Microelectronics Course2001 International Conference on Microelectronic Systems Education (MSE 2001), IEEE Computer Society, Los Alamitos, USA (71-72)
      ISBN: 0769511562
    • Kropp, H.; Schwiegershausen, M.; Do, -.; Reuter, C.; Pirsch, P. (1997): Entwurf von High-Performance-Multiplizierern für Xilinx FPGAs4. SICAN Herbsttagung, Mikroelektronik-Mikrosysteme, (119-122)
    • Friebe, L.; Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2001): Multi-DSP-Board for Compact Real-Time Synthetic Aperture Radar SystemsAerosense Conference Proceedings on Technologies for Synthetic Environments: Hardware-in-the-Loop Testing VI, SPIE, Bellingham
      ISBN: 0819440612
    • Stolberg, -.; Berekovic, M.; Pirsch, P.; Runge, H. (2001): Implementing the MPEG-4 Advanced Simple Profile for Streaming Video ApplicationsProceedings International Conference on Multimedia and EXPO (ICME2001), IEEE Press, Piscataway, USA (297-300)
      ISBN: 0769511988
    • Stolberg, -.; Berekovic, M.; Pirsch, P.; Runge, H. (2001): The MPEG-4 Advanced Simple Profile - A Complexity StudyProceedings of the 2nd Workshop and Exhibition on MPEG-4, n/a (33-36)
      ISBN: n/a
    • Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Friebe, L.; Klar, C.; Pirsch, P. (2002): HIPAR-DSP 16, A SCALABLE HIGHLY PARALLEL DSP CORE FOR SYSTEM ON A CHIP VIDEO- AND IMAGE PROCESSING APPLICATIONSAcoustics, Speech, and Signal Processing, 2002 IEEE International Conference on, Volume 3, IEEE, Piscataway (CD-ROM)
      ISBN: 0780374029
    • Kloos, H.; Friebe, L.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2001): HiPAR-DSP 16, A new DSP for Onboard Real-Time SAR SystemsAerosense Conference Proceedings on Photonic and Quantum Technologies for Aerospace Applications III, SPIE, Bellingham
      ISBN: 0819440817
    • Friebe, L.; Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Klar, C.; Pirsch, P. (2001): A Compact Real-Time SAR Processing System using the Highly Parallel HiPAR-DSP 16International Geoscience and Remote Sensing Symposium 2001, IEEE, Piscataway (CD-ROM)
      ISBN: 0780370333
    • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2013): FPGA-based Architecture for real-time SAR processing with integrated Motion CompensationThe 4th Asia-Pacific Conference on Synthetic Aperture Radar (APSAR)
    • Berekovic, M.; Stolberg, -.; Pirsch, P.; Runge, H. (2001): A Programmable Co-Processor for MPEG-4 VideoInternational Conference on Acoustics, Speech and Signal Processing, IEEE Press, Piscataway, NJ (CD-ROM)
      ISBN: 0780370414
    • Banz, C.; Blume, H.; Pirsch, P. (2012): Evaluation of penalty functions for SGM cost aggregationIntl. Archives of Photogrammetry and Remote Sensing
    • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2012): Close-to-hardware error analysis for real-time wavenumber domain processingRADAR 2012, 7th International Conference on Radar
    • Nolte, N.; Moch, S.; Kock, M.; Pirsch, P. (2009): Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreamsAnnual IEEE International SoC Conference, SoCC 2009, Belfast, Northern Ireland, UK, Proceedings, (427-431)
    • Ohmacht, M.; Stolberg, -.; Pirsch, P. (1998): Adaptive Resource Utilization in Cellular Multiprocessor ArraysProceedings 6th IEEE International Workshop on Intelligent Signal Processing and Communication Systems, (571-575)
    • Stolberg, -.; Ohmacht, M.; Pirsch, P. (1998): Dynamic Task Migration in Cellular Multiprocessor ArraysProceedings 2nd IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'98), (206-209)
    • Wittenburg, P.; Meyer, G.; Pirsch, P. (1999): Adapting and Extending Simultaneous Multithreading for High Performance Video Signal Processing ApplicationsWorkshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC)
    • Stolberg, -.; Ohmacht, M.; Pirsch, P. (1999): Cellular Multiprocessor Arrays with Adaptive Resource UtilizationParallel Computation: Proceedings 4th International ACPC Conference, (480-489)
    • Hilgenstock, J.; Herrmann, K.; Pirsch, P. (1999): Memory Organzation of a Single-Chip Video Signal Processing System with Embedded DRAM9th Great Lakes Symposium on VLSI, (42-45)
    • Berekovic, M.; Jacob, K.; Pirsch, P. (1999): Architecture of a Hardware Module for MPEG-4 Shape DecodingProceedings of ISCAS'99, (157-160)
    • Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (1999): A High Performance Digital Signal Processor for Compact Realization of Real-Time Synthetic Aperture Radar SystemsInternational Geoscience and Remote Sensing Symposium Proceedings, (CD-ROM)
    • Kropp, H.; Reuter, C.; Pirsch, P. (1999): An FPGA-based Prototyping System for Video Processing SchemesProceedings 9th International Workshop on Field Programmable Logic and Applications (FPL'99), (333-338)
    • Hinrichs, W.; Wittenburg, P.; Lieske, H.; Kloos, H.; Ohmacht, M.; Pirsch, P. (1999): A 1.3 GOPS Parallel DSP for High Performance Image Processing ApplicationsProceedings of the 25th European Solid-State Circuits Conference (ESSCIRC), (102-105)
    • Septinus, K.; Dragone, S.; Langner, M.; Blume, H.; Pirsch, P. (2011): A Scalable Hardware Algorithm for Demanding Timer Management in Network Systems24. PARS - Workshop am 26./27. Mai 2011, Rüschlikon, Switzerland, PARS Mitteilungen GI, ISSN 0177-0454
    • Berekovic, M.; Heistermann, D.; Pirsch, P. (1998): A Core Generator for Fully Synthesizable and Highly Parameterizable RISC-Cores for Systems-On-Chip Designs1998 IEEE Workshop on Signal Processing Systems (SiPS '98), (561-568)
    • Do, T.; Kropp, H.; Reuter, C.; Pirsch, P. (1998): A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAsLecture Notes in Computer Science: Field Programmable Logic and Applications (8th International Workshop FPL'98), 1482, R. W. Hartenstein, A. Keevallik, (441-445)
    • Kropp, H.; Reuter, C.; Pirsch, P. (1998): The Video and Image Processing Emulation System VIPESNinth IEEE International Workshop on Rapid System Prototyping, (170-175)
    • Wittenburg, P.; Hinrichs, W.; Kneip, J.; Ohmacht, M.; Berekovic, M.; Lieske, H.; Kloos, H.; Pirsch, P. (1998): Realization of a Programmable Parallel DSP for High Performance Image Processing ApplicationsDesign Automation Conference (DAC) 1998, (56-61)
    • Hilgenstock, J.; Herrmann, K.; Otterstedt, J.; Niggemeyer, D.; Pirsch, P. (1998): A Video Signal Processor for MIMD MultiprocessingDesign Automation Conference (DAC) 1998, (50-55)
    • Langemeyer, S.; Pirsch, P.; Blume, H. (2011): A FPGA architecture for real-time processing of variable-length FFTs2011 International Conference on Acoustics, Speech and Signal Processing, ICASSP, IEEE (8)
    • Berekovic, M.; Pirsch, P. (1998): An Array Processor with Parallel Data Cache for Image Rendering and CompositingProceedings of Computer Graphics International CGI98, (411-414)
    • Ohmacht, M.; Wittenburg, P.; Pirsch, P. (1998): Influences of Object Based Segmentation onto Multimedia Hardware ArchitecturesInternational Symposium on Circuits and Systems, 4, (45-48)
    • Pfitzner, M.; Langemeyer, S.; Pirsch, P.; Blume, H. (2011): A flexible real-time SAR processing platform for high resolution airborne image generationRADAR 2011, 6th International Conference on Radar
    • Pirsch, P.; Stolberg, J. (1998): VLSI Architectures for MultimediaInternational Conference on Electronics, Circuits and Systems, 1, (3-11)
    • Berekovic, M.; Pirsch, P. (1998): Architecture of a Coprocessor Module for Image CompositingInternational Conference on Electronics, Circuits and Systems, 2, (203-206)
    • Kropp, H.; Reuter, C.; Do, T.; Pirsch, P. (1998): A Generator for Pipelined Multipliers on FPGAs9th International Conference on Signal Processing Applications and Technology, 1, (669-673)
    • Herrmann, K.; Hilgenstock, J.; Pirsch, P. (1998): A Single Chip Video Coding System with Embedded DRAM Frame Memory for Stand-Alone Applications11th IEEE Int. ASIC Conference 1998, (319-323)
    • Kloos, H.; Berekovic, M.; Pirsch, P. (1999): Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-AnwendungenArchitektur von Rechnersystemen (ARCS'99), (5-15)
    • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2012): A flexible hardware architecture for real-time airborne Wavenumber Domain SAR processing9th European Conference on Synthetic Aperture Radar
    • Wittenburg, J.; Hinrichs, W.; Ohmacht, M.; Lieske, H.; Kloos, H.; Pirsch, P. (1999): HiPAR-DSP: Ein 1.3 GOPS Multimedia SignalprozessorArchitektur von Rechensystemen (ARCS '99) GI/ITG Fachtagung, (15-21)
    • Banz, C.; Blume, H.; Pirsch, P. (2011): Real-Time Semi-Global Matching Disparity Estimation on the GPUWorkshop on GPU in Computer Vision Applications @ International Conference on Computer Vision (ICCV), IEEE (514-521)
    • Berekovic, M.; Pirsch, P.; Selinger, T.; Wels, -.; Lafage, A.; Miro, C.; Ghigo, G.; Heer, C. (1999): The TANGRAM co-processor for MPEG-4 Visual Compositing1999 IEEE Workshop on Signal Processing Systems (SiPS'99), (311-320)
    • Wittenburg, P.; Pirsch, P.; Meyer, G. (1999): A Multithreaded Architecture Approach to Parallel DSPs for High Performance Image Processing Applications1999 IEEE Workshop on Signal Processing Systems (SiPS '99), (241-250)
    • Pirsch, P. (1999): Architectures for Multimedia Signal ProcessingProceedings 1999 IEEE Workshop on Signal Processing Systems (SiPS'99), (1-12)
    • Berekovic, M.; Lieske, H.; Kloos, H.; Pirsch, P. (1999): Branch Prediction for a SIMD DSP Array ProcessorInternational Conference on Signal Processing Applications and Technology (ICSPAT), (CD-ROM)
    • Hinrichs, W.; Wittenburg, P.; Lieske, H.; Kloos, H.; Ohmacht, M.; Pirsch, P. (1999): A Parallel DSP for High Performance Image Processing ApplicationsInternational Conference on Signal Processing Applications and Technology Proceedings 1999 (ICSPAT), (CD-ROM)
    • Lieske, H.; Wittenburg, J.; Hinrichs, W.; Kloos, H.; Ohmacht, M.; Pirsch, P. (1999): Enhancements for a Second Generation Parallel Multimedia-DSP1st Workshop on Media Processors and DSPs (MP-DSP), (68-77)
    • Berekovic, M.; Stolberg, -.; Pirsch, P.; Möller, H.; Runge, H.; Kneip, J. (1999): The MPIRE MPEG-4 Codec DSP1st Workshop on Media Processors and DSPs (MP-DSP), (62-67)
    • Banz, C.; Flatt, H.; Blume, H.; Pirsch, P. (2009): Hardware-Architektur zur echtzeitfähigen Berechnung dichter DisparitätskartenITG Fachtagung für Elektronische Medien "Systeme, Technologien, Anwendungen" 13. Dortmunder Fernsehseminar, VDE
    • Payá-Vayá, G.; Martín-Langerwerf, J.; Taptimthong, P.; Pirsch, P. (2007): Design Space Exploration of Media Processors: A Parameterized SchedulerProceedings of the Intl. Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), IEEE (41-49)
      DOI: 10.1109/ICSAMOS.2007.4285732
      ISBN: 1424410584
    • Payá-Vayá, G.; Jambor, T.; Septinus, K.; Hesselbarth, S.; Flatt, H.; Freisfeld, M.; Pirsch, P. (2007): CHIPDESIGN - From Theory to Real WorldProceedings of the Workshop on Computer Architecture Education in conjunction with the 34th International Symposium on Computer Architecture, ACM (58-64) Weitere Informationen
      ISBN: 978-1-59593-797-1
    • Payá-Vayá, G.; Langerwerf, M.; Pirsch, P. (2007): Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized SchedulerARCS 2007, LNCS 4415, Springer-Verlag, Berlin Heidelberg (254-267)
      DOI: 10.1007/978-3-540-71270-1_19
      ISBN: 3540712674
    • Simon-Klar, C.; Nolte, N.; Langemeyer, S.; Pirsch, P. (2006): Image Data Rate Reduction for an On-Board Real-Time SAR-ProcessorProceedings of EUSAR 2006, VDE-Verlag GmbH, Berlin, Offenbach (CDROM)
      ISBN: 3800729601
    • Flügel, S.; Klußmann, H.; Pirsch, P.; Schulz, M.; Cisse, M.; Gehrke, W. (2007): A highly parallel sub-pel accurate motion estimator for H.264IEEE 2006 International Workshop on Multimedia Signal Processing (MMSP-06)
    • Payá-Vayá, G.; Martín-Langerwerf, J.; Pirsch, P. (2007): RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip10th EUROMICRO Conference on Digital System Design (DSD 2007): Architectures, Methods and Tools, IEEE Conference Publishing Services, Los Alamitos (California, USA) (215-221)
      DOI: 10.1109/DSD.2007.4341471
      ISBN: 9780769529783
    • Flatt, H.; Blume, S.; Tarnowsky, A.; Blume, H.; Pirsch, P. (2009): Echtzeitfähige Abbildung eines videobasierten Objekterkennungsalgorithmus auf eine modulare Coprozessor-ArchitekturITG Fachtagung für Elektronische Medien "Systeme, Technologien, Anwendungen" 13. Dortmunder Fernsehseminar, VDE
    • Flatt, H.; Blume, S.; Hesselbarth, S.; Schünemann, T.; Pirsch, P. (2008): A Parallel Hardware Architecture for Connected Component Labeling Based on Fast Label MergingInternational Conference on Application-specific Systems, Architectures and Processors, ASAP, IEEE
      DOI: 10.1109/ASAP.2008.4580169
      ISBN: 978-1-4244-1897-8
    • Septinus, K.; Mayer, U.; Starke, W.; Pirsch, P. (2008): Design of a (B)FSM-based Processing EngineCOOL Chips XI, International Symposium on Low-Power and High-Speed Chips, (132)
    • Septinus, K.; Le, T.; Mayer, U.; Pirsch, P. (2007): On the Design of Scalable Massively Parallel CRC CircuitsProceedings of 2007 IEEE International Conference on Electronics, Circuits and Systems, (142-145)
    • Langemeyer, S.; Simon-Klar, C.; Nolte, N.; Pirsch, P. (2005): Architecture of a Flexible On-Board Real-Time SAR-ProcessorIGARSS 2005, IEEE (CD-ROM)
      ISBN: 0780390512
    • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2013): Development and Potential of Real-Time FPGA Frequency-Based SAR Image Processing for Short-Range FMCW ApplicationsThe 2013 International Conference on Radar (RADAR2013)
    • Berekovic, M.; Moch, S.; Pirsch, P. (2003): A Scalable, Clustered SMT Processor for Digital Signal ProcessingMedea Workshop (in conjunction with PACT)
    • Stolberg, -.; Moch, S.; Friebe, L.; Dehnhardt, A.; Kulaczewski, B.; Berekovic, M.; Pirsch, P. (2004): An SoC with Two Multimedia DSPs and a RISC Core for Video Compression Applications2004 IEEE International Solid-State Circuits Conference Digest of Technical Papers, IEEE, Piscataway, NJ (330-331, 531)
      ISBN: 01936530
    • Simon-Klar, C.; Kirscht, M.; Langemeyer, S.; Nolte, N.; Pirsch, P. (2004): An On-board Real-Time SAR Processor for Small PlatformsProceedings of SPIE Vol. 5574, Remote Sensing for Environmental Monitoring, GIS Applications, and Geology IV, SPIE, Bellingham, WA (420-427)
      ISBN: ISBN 0819455210
    • Jachalsky, J.; Wahle, M.; Pirsch, P.; Gehrke, W.; Hinz, T. (2004): A Coprocessor for Intelligent Image and Video Processing in the Automotive and Mobile Communication Domain2004 IEEE International Symposium on Consumer Electronics. Proceedings, IEEE Press, Piscataway, NJ (142-145)
      ISBN: 0780385268
    • Simon-Klar, C.; Kirscht, M.; Langemeyer, S.; Nolte, N.; Pirsch, P. (2004): A Small Real-Time Processor for SAR Image GenerationProceedings EUSAR 2004 5th European Conference on Synthetic Aperture Radar, VDE Verlag GmbH, Berlin (729-732)
      ISBN: 3800728281
    • Moch, S.; Berekovic, M.; Stolberg, -.; Friebe, L.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core Architecture for Image and Video ApplicationsProceedings MEDEA Workshop at The Twelfth International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), (57-63)
    • Pirsch, P.; Gehrke, W.; Gaedke, K.; Herrmann, K. (1994): A parallel VLSI Architecture for Object Based Analysis-Synthesis Video CodingIEEE Workshop on Visual Signal Processing and Communications, (136-141)
    • Pirsch, P.; Gehrke, W. (1995): VLSI Architectures for Video Signal ProcessingIEE Image Processing and its Applications, (6-10)
    • Pirsch, P.; Gehrke, W. (1995): VLSI Architectures for Video CompressionProceedings ISSSE '95, (49-54)
    • Kneip, J.; Wittenburg, P.; Berekovic, M.; Rönner, K.; Pirsch, P. (1995): An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal ProcessorVLSI Signal Processing VIII, (41-51)
    • Pirsch, P.; Kneip, J.; Rönner, K. (1995): Parallelization Resources of Image Processing Algorithms and their Mapping on a Programmable Parallel Videosignal ProcessorIEEE International Symposium on Circuits and Systems, (562-565)
    • Schwiegershausen, M.; Pirsch, P. (1995): A Formal Approach for the Optimization of Heterogeneous Multiprocessors for Complex Image Processing SchemesProceedings of EURO-DAC '95, IEEE Computer Society Press (8-13)
    • Schwiegershausen, M.; Pirsch, P. (1995): A System level Design Methodology for the Optimization of Heterogeneous MultiprocessorsProceedings of 8th International Symposium on System Synthesis, IEEE Computer Society Press (162-167)
    • Schwiegershausen, M.; Kropp, H.; Pirsch, P. (1996): A System Level HW/SW-Partitioning and Optimization ToolEuropean Design Automation Conference (EDAC), (120-125)
    • Herrmann, K.; Hilgenstock, J.; Gaedke, K.; Jeschke, H.; Pirsch, P. (1996): A Programmable Processing Element Dedicated as Building Block for a Large Area Integrated Multiprocessor SystemIEEE International Conference: Innovative Systems in Silicon, (98-103)
    • Herrmann, K.; Gaedke, K.; Hilgenstock, J.; Pirsch, P. (1996): Design of a Development System for Multimedia Applications based on a Single Chip Multiprocessor ArrayICECS, (1151-1154)
    • Pirsch, P.; Gehrke, W. (1995): VLSI Architectures for Video Signal ProcessingVisual Communications and Image Processing 1995, SPIE, 2501, (758-777)
    • Gaedke, K.; Herrmann, K.; Jeschke, H.; Pirsch, P. (1995): AxPe640V - Ein hochintegrierter Videosignalprozessor für die Echtzeit-VideocodierungGME-Fachbericht Mikroelektronik, 15, VDE-Verlag (69-74)
    • Septinus, K.; Nowosielski, R.; Pirsch, P.; Blume, H. (2009): Simulation and Modeling of I/O Protocol Processing with Application of Network Interface Design ExplorationProRISC 2009. 20th Annual Workshop on Circuits, Systems and Signal Processing, (515-521)
    • Pirsch, P.; Gehrke, W. (1994): VLSI-Realisierungen für MPEG-VideoMikroelektronik für die Informationstechnik, ITG-Fachbericht 127, VDE-Verlag GmbH (143-152)
    • Gehrke, W.; Hoffer, R.; Pirsch, P. (1994): A Hierarchical Multiprocessor Architecture based on Heterogeneous Processors for Video Coding ApplicationsInternational Conference on Acoustics, Speech and Signal Processing, (II 413-416)
    • Payá-Vayá, G.; Martín-Langerwerf, J.; Giesemann, F.; Blume, H.; Pirsch, P. (2009): Instruction Merging to Increase Parallelism in VLIW ArchitecturesInternational Symposium on System-on-Chip 2009, Intl. Symposium on System-on-Chip, J. Nurmi, J. Takala, O. Vainio, IEEE (143-146)
      DOI: 10.1109/SOCC.2009.5335660
      ISBN: 978-1-4244-4465-6
    • Kneip, J.; Rönner, K.; Pirsch, P. (1994): A Single Chip Parallel Architecture for Image Processing ApplicationsSPIE - Visual Communications and Image Processing '94, 2308, (1753-1764)
    • Flatt, H.; Schmädecke, I.; Kärgel, M.; Blume, H.; Pirsch, P. (2009): Hardware-Based Synchronization Framework for Heterogeneous RISC/Coprocessor ArchitecturesInternational Symposium on Systems, Architectures, Modeling, and Simulation, SAMOS, IEEE (125-132)
      DOI: 10.1109/ICSAMOS.2009.5289223
    • Langemeyer, S.; Pirsch, P.; Blume, H. (2011): Using SDRAMs for two-dimensional accesses of long 2^n x 2^m-point FFTs and transposingConference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS, IEEE
    • Kneip, J.; Rönner, K.; Pirsch, P. (1994): A Data Path Array with Shared Memory as Core of a High Performance DSPThe International Conference on Application Specific Array Processors, IEEE Computer Society Press (271-282)
    • Nolte, N.; Gehrke, W.; Wiczinowski, F.; Pirsch, P. (2007): SCALABLE MULTI-STANDARD LSI TEXTURE ENCODER FOR MPEG AND VC-1 VIDEO COMPRESSIONMultimedia and Expo, 2007 IEEE International Conference on, (1187-1190)
      DOI: 10.1109/ICME.2007.4284868
      ISBN: 1-4244-1016-9
    • Pirsch, P.; Gehrke, W.; Gaedke, K.; Herrmann, K. (1994): A Parallel VLSI Architecture for Object-based Analysis-Synthesis CodingIEEE Workshop Visual Signal Processing and Image Communications, (136-141)
    • Herrmann, K.; Seifert, M.; Gaedke, K.; Jeschke, H.; Pirsch, P. (1994): Architecture and VLSI Implementation of a RISC Core for a Monolithic Video Signal ProcessorVLSI Signal Processing VII, J. Rabaey, P. M. Chau, J. Eldon, IEEE (368-377)
    • Schwiegershausen, M.; Pirsch, P. (1994): Optimization of Heterogeneous Multiprocessors for Complex Image Processing ApplicationsProceedings of the IFIP Workshop on Logic and Architecture Synthesis, (251-260)
    • Payá-Vayá, G.; Martín-Langerwerf, J.; Blume, H.; Pirsch, P. (2010): A Forwarding-sensitive Instruction Scheduling Approach to Reduce Register File Constraints in VLIW ArchitecturesApplication-specific Systems, Architectures and Processors, 2010. ASAP 2010. 21th IEEE International Conference on, François Charot, Frank Hannig, Jürgen Teich, and Christophe Wolinski, IEEE (151-158)
      ISBN: 978-1-4244-6965-9
    • Herrmann, K.; Gaedke, K.; Pirsch, P. (1995): Design eines Entwicklungssystems für Multi-Media-Anwendungen auf Basis des programmierbaren Videosignalprozessors AxPe640V6. Dortmunder Fernsehseminar, ITG-Fachbericht, (136), VDE-Verlag (151-156)
    • Septinus, K.; Mayer, U.; Pirsch, P.; Blume, H. (2010): A Fully Programmable FSM-based Processing Engine for Gigabytes/s Header Parsing2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IEEE (45-54)
      ISBN: 978-1-4244-7937-5
    • Winzker, M.; Pirsch, P.; Reimers, J. (1995): Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMsProc. of IEEE Intl. Symposium on Circuits and Systems (ISCAS), (609-612)
    • Banz, C.; Hesselbarth, S.; Flatt, H.; Blume, H.; Pirsch, P. (2010): Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-ImplementationInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, (SAMOS X), IEEE (93-101)
      DOI: 10.1109/ICSAMOS.2010.5642077
    • Stolberg, -.; Berekovic, M.; Friebe, L.; Moch, S.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal ProcessingProceedings 2003 IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Technische Universität Darmstadt, Institute of Microelectronic Systems (155-160)
      ISBN: 3901882170
    • Payá-Vayá, G.; Martín-Langerwerf, J.; Banz, C.; Giesemann, F.; Pirsch, P.; Blume, H. (2010): VLIW Architecture Optimization for an Efficient Computation of Stereoscopic Video ApplicationsThe 2010 International Conference on Green Circuits and Systems, IEEE (457-462)
      ISBN: 978-1-4244-6877-5
    • Herrmann, K.; Gaedke, K.; Jeschke, H.; Pirsch, P. (1996): A Monolithic Low Power Video Signal Processor for Multimedia ApplicationsInternational Conference on Consumers Electronics (ICCE), (176-177)
    • Kneip, J.; Wittenburg, P.; Hinrichs, W.; Berekovic, M.; Pirsch, P. (1996): Der HiPAR-DSP: Ein programmierbarer monolithischer Parallelprozessor für die EchtzeitbildverarbeitungIGT-Fachbericht, VDE-Verlag GmbH (55-60)
    • Herrmann, K.; Hilgenstock, J.; Pirsch, P. (1997): Architecture of a Multiprocessor System with Embedded DRAM for Large Area IntegrationProceedings of the International Conference on Innovative Systems in Silicon 1997, (274-281)
    • Berekovic, M.; Kloos, H.; Pirsch, P. (1997): Hardware Realization of a JAVA Virtual Machine for High Performance Multimedia Applications1997 IEEE Workshop on Signal Processing Systems (SiPS '97), M. K. Ibrahim, P. Pirsch, J. McCanny, (479-488)
    • Hilgenstock, J.; Herrmann, K.; Wallenberg, v.; Pirsch, P. (1997): Implementation of a Multiprocessor System for Real-Time Video Signal ProcessingProceedings of the International Conference on Electronics, Circuits and Systems (ICECS) 1997, (1423-1426)
    • Wittenburg, P.; Ohmacht, M.; Kneip, J.; Hinrichs, W.; Pirsch, P. (1997): HiPAR-DSP: A Parallel VLIW RISC Processor for Real Time Image Processing ApplicationsProceedings of the International Conference on Algorithms And Architectures for Parallel Processing (ICA3PP) 1997, (155-162)
    • Freimann, A.; Brune, T.; Pirsch, P. (1998): Mapping of Video Decoder Software on a VLIW DSP MultiprocessorMultimedia Hardware Architectures, Proceedings of SPIE, 3311, (67-78)
    • Berekovic, M.; Meyer, G.; Guo, Y.; Pirsch, P. (1998): A Multimedia RISC Core for Efficient Bitstream Parsing and VLDMultimedia Hardware Architectures, Proceedings of SPIE, 3311, (131-141)
    • Payá-Vayá, G.; Martín-Langerwerf, J.; Moch, S.; Pirsch, P. (2009): An Enhanced DMA Controller in SIMD Processors for Video ApplicationsArchitecture of Computing Systems - ARCS 2009, Lecture Notes in Computer Science(Vol. 5455/2009), Berekovic et al., Springer Berlin / Heidelberg (159-170)
      DOI: 10.1007/978-3-642-00454-4_17
      ISBN: 978-3-642-00453-7
    • Flatt, H.; Blume, H.; Pirsch, P. (2010): Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD ResolutionInternational Conference on Reconfigurable Computing, ReConFig, IEEE (452-457)
      DOI: 10.1109/ReConFig.2010.16
    • Do, T.; Kropp, H.; Reuter, C.; Schwiegershausen, M.; Pirsch, P. (1998): Implementierung von Pipeline-Multiplizierern auf Xilinx FPGAsITG Fachbericht 147, ITG Fachtagung Mikroelektronik für die Informationstechnik 1998, (83-88)
    • Berekovic, M.; Kloos, H.; Pirsch, P. (1998): Parallele Implementierung einer JAVA Virtual Machine mit Erweiterungen für MultimediaITG Fachbericht 147, ITG Fachtagung Mikroelektronik für die Informationstechnik 1998, (305-310)
    • Berekovic, M.; Pirsch, P.; Selinger, T.; Wels, -.; Miro, C.; Lafage, A.; Heer, C.; Ghigo, G. (2000): Architecture of an Image Rendering Co-Processor for MPEG-4 SystemsProceedings of ASAP 2000, IEEE Computer Society, Los Alamitos, California (15-24)
      ISBN: 0769507166
    • Hinrichs, W.; Wittenburg, P.; Ohmacht, M.; Kneip, J.; Pirsch, P. (1998): HiPAR-DSP: Ein paralleler VLIW RISC-Prozessor für die EchtzeitbildverarbeitungITG Fachbericht 147, ITG Fachtagung Mikroelektronik für die Informationstechnik 1998, (257-262)
    • Herrmann, K.; Moch, S.; Hilgenstock, J.; Pirsch, P. (2000): Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated CircuitProceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2000), IEEE Computer Society, Los Alamitos, California (105-113)
      ISBN: 0769507190
    • Do, T.; Kropp, H.; Schwiegershausen, M.; Pirsch, P. (1997): Implementation of Pipelined Multipliers on Xlinix FPGAsProceedings of the 7th International Workshop Field-Programmable Logic and Applications (FPL '97), W. Luk, P. Y. K. Cheung, M. Glesner, Springer Verlag (51-60)
    • Reuter, C.; Schwiegershausen, M.; Pirsch, P. (1997): Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary AlgorithmsProceedings of the 1997 International Conference on Application Specific Systems, Architectures, and Processors (ASAP), (294-303)
    • Wittenburg, P.; Hinrichs, W.; Lieske, H.; Kloos, H.; Friebe, L.; Pirsch, P. (2000): HiPAR-DSP - a Scalable Family of High Performance DSP-CoresProceedings of the 13th Annual IEEE International ASIC/SOC Conference, Institute of Electrical and Electronics Engineers, Inc (IEEE); Piscataway, NJ (92-96)
      ISBN: 0780365984
    • Kropp, H.; Schwiegershausen, M.; Pirsch, P. (1996): A CAD Tool for the Optimization of Video Signal Processor ArchitecturesProceedings of ICASSP96, IEEE Computer Society Press (1244-1247)
    • Berekovic, M.; Stolberg, -.; Pirsch, P.; Selinger, T.; Wels, -.; Miro, C.; Lafage, A.; Heer, C.; Ghigo, G. (2000): Co-Processor Architecture for MPEG-4 Main Profile Visual CompositingProceedings International Symposium on Circuits and Systems (ISCAS), IEEE Press, Piscataway, NJ (II 180-183)
      ISBN: 0780354826
    • Kneip, J.; Pirsch, P. (1996): Memory Efficient List Based Hough Transform for Programmable Digital Signal Processors with On-Chip CachesProc. 1996 IEEE Digital Signal Processing Workshop, (191-194)
    • Stolberg, -.; Berekovic, M.; Pirsch, P.; Runge, H.; Möller, H.; Kneip, J. (2000): The M-PIRE MPEG-4 CODEC DSP and its Macroblock EngineProceedings IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Press, Piscataway, NJ (II 192-195)
      ISBN: 0780354826
    • Kneip, J.; Pirsch, P. (1996): An Object Based Data Cache with Conflict Free Access as Shared Memory of a Parallel DSPProc. 1996 IEEE Intern. Workshop on VLSI Signal Processing IX, (25-34)
    • Pirsch, P. (1977): Block Coding of Color Video SignalsNTC Conference Record, (10:5.1-10:5.5)
    • Winter, M.; Schwiegershausen, M.; Pirsch, P. (1996): Ein CAD-Tool zur Optimierung heterogen aufgebauter Multiprozessoren3. SICAN Herbsttagung, (19-24)
    • Pirsch, P. (1979): Design of DPCM Quantizers for Video Signals Using Subjective TestsPicture Coding Symposium
    • Kneip, J.; Ohmacht, M.; Wittenburg, P.; Pirsch, P. (1996): Parallel Implementations of Medium Level Algorithms on a Monolithic ASIMD MultiprocessorProceedings of ISCAS '96, 4, IEEE Press (316-319)
    • Pirsch, P. (1979): A New Predictor Design for DPCM CodersPicture Coding Symposium
    • Pirsch, P.; Freimann, A.; Berekovic, M. (1997): Architectural approaches for multimedia processorsIS&T/SPIE Conference: Multimedia Hardware Achitectures, SPIE, 3021, (2-13)
    • Pirsch, P. (1980): A New Predictor Design for DPCM Coding of TV SignalsICC'80 Conference Record, (31.2.1-31.2.5)
    • Hilgenstock, J.; Herrmann, K.; Pirsch, P. (1997): A Parallel DSP Architecture for Object-based Video Signal ProcessingIS&T/SPIE Conference: Multimedia Hardware Architectures, SPIE, 3021, (78-87)
    • Kneip, J.; Pirsch, P. (1997): Object Oriented Cache Architectures with Parallel Access as On-Chip Memories for Programmable DSPsMikroelektronik'97 - GMM Fachbericht, (149-156)
    • Kneip, J.; Berekovic, M.; Pirsch, P. (1997): An Algorithm-Hardware-System Approach to VLIW Multimedia ProcessorsProceedings of the 1997 IEEE Workshop on Multimedia Signal Processing, Y. Wang, A. R. Reibmann, B. H. Juang, T. Chen, S. Y. Kung, (433-438)
    • Pirsch, P.; Stolberg, J. (1997): Architectural Approaches for Video CompressionProceedings of the 1997 International Conference on Application Specific Systems, Architectures, and Processors (ASAP), (176-185)
    • Berekovic, M.; Frase, R.; Pirsch, P. (1998): A Flexible Processor Architecture for MPEG-4 Image CompositingProceedings of ICASSP'98
    • Do, -.; Kropp, H.; Reuter, C.; Pirsch, P. (1998): Alternative Approaches Implementing High-Performance FIR Filters on Lookup Table-Based FPGAs: A ComparisonProceedings of the SPIE (3526): Configurable Computing: Technology and Applications, SPIE, Bellingham (248-254)
      ISBN: 0819429872
    • Schönfeld, M.; Schwiegershausen, M.; Pirsch, P. (1991): Synthesis of Intermediate Memories needed for the Data Supply to Processor ArraysProc. of VLSI, Halaas, Denyer, (7.3.1-7.3.10)
    • Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Friebe, L.; Pirsch, P. (2000): HiPAR-DSP 16 A Parallel DSP for Onboard Real-Time Processing of Synthetic Aperture Radar DataInternational Geoscience and Remote Sensing Symposium Proceedings 2000, IEEE, Piscataway, NY, USA (CD-ROM)
    • Schönfeld, M.; Pirsch, P.; Schwiegershausen, M. (1991): Synthesis of Intermediate Memories needed to handle the Data Supply to Processor ArraysFifth International ACM & IEEE Workshop on High-Level Synthesis, W. Rosenstiel, (21-28)
    • Rönner, K.; Hecht, V.; Pirsch, P. (1991): Defekttoleranter systolischer Arrayprocessor für die zweidimensionale Faltung von BildsequenzenGME-Fachtagung Mikroelektronik, GME-Fachbericht 8, (95-100)
    • Hilgenstock, J.; Herrmann, K.; Moch, S.; Pirsch, P. (2000): A Single-Chip Video Signal Processing System with Embedded DRAMIEEE Workshop on Signal Processing Systems 2000 (SIPS), IEEE Press, Piscataway, NJ (23-32)
      ISBN: 0780364880
    • Pirsch, P.; Jeschke, H. (1991): A MIMD multiprocessor system for real-time image processingProc. of the SPIE / SPSE Symposium on Electronic Imaging: Science & Technology, 1452, (544-555)
    • Pirsch, P. (1991): VLSI Architectures and Implementations for Digital Video CodingProc. of Congress: Innovative Developments and Applications of Microelectronics and Information Technologie, E. Raubold, VDE-Verlag GmbH (439-445)
    • Pirsch, P. (1981): Adaptive Intra-Interframe PrädiktorenSummaries of the 4. Aachener Kolloquium, (163-166)
    • Pirsch, P. (1981): Stability Conditions of DPCM CodersPicture Coding Symposium
    • Pirsch, P.; Komarek, T. (1988): VLSI Architectures for Block Matching AlgorithmsProc. SPIE Conf. Visual Communications and Image Processing III, (882-891)
    • Pirsch, P. (1988): VLSI-Realisierungen für die VideocodierungITG-Fachtagung Mikroelektronik für die Informationstechnik, ITG Fachbericht 103, (119-126)
    • Pirsch, P.; Schönfeld, J. (1989): VLSI realization of low level image processing unitsProc. of the PROMETHEUS Workshop, (246-253)
    • Schönfeld, J.; Pirsch, P. (1990): VLSI Implementation for Real Time Processing of Straight Line ExtractionFrom Pixels to Features II, J. C. Simon, Elsevier (395-406)
    • Münzner, A.; Pirsch, P. (1989): BADGE - Building Block Adviser and GeneratorProc. of IEEE Int. Symp. on Circuits and Systems, 3, (1887-1890)
    • Rönner, K.; Hecht, V.; Pirsch, P. (1990): Defect-Tolerant Implementation of a Systolic Array for Two-Dimensional ConvolutionProc. of IEEE Intl. Conf. on Wafer Scale Integration, IEEE Comp. Soc. Press (19-25)
    • Münzner, A.; Pirsch, P. (1989): BADGE: Ein Programm zur Buildingblock-GenerierungITG-Fachtagung Mikroelektronik für die Informationstechnik, ITG-Fachbericht 110, (35-40)
    • Pirsch, P.; Wehberg, T. (1990): VLSI Architecture of a Programmable Real-Time Video Signal ProcessorProc. SPIE Digital Image Processing and Visual Communications Technologies in the Earth and Athmospheric Sciences, (2-12)
    • Grüger, K.; Pirsch, P. (1989): Architecture of a 560 Mbit/s DPCM-HDTV-CodecProc. Third Int. Workshop on HDTV, II
    • Komarek, T.; Pirsch, P. (1989): VLSI architectures for block matching algorithmsFirst ESA Workshop on Digital Signal Processing Techniques applied to Space Applications
    • Komarek, T.; Pirsch, P. (1990): VLSI Architectures for hierarchical Block Matching AlgorithmsProc. IEEE, Int. Symposium on Circuits and Systems, (45-48)
    • Komarek, T.; Pirsch, P. (1989): VLSI Architectures for Block Matching AlgorithmsProc. IEEE Int. Conf on Acoustics, Speech & Signal Processing (ICASSP), (2457-2460)
    • Pirsch, P.; Heiß, R. (1987): Compact video codec for broadband communicationsConference Record TV Symposium Montreux, (206-219)
    • Grüger, K.; Pirsch, P.; Kraus, J.; Reimers, J. (1990): VLSI components for a 560 Mbit/s HDTV codecProc. SPIE Conf. Visual Communications and Image Processing, (388-397)
    • Pirsch, P.; Kemper, A. (1987): HALMA: A program for logic synthesis considering application specific constraintsInternational Workshop on Logic Synthesis
    • Grüger, K.; Pirsch, P. (1990): VLSI-Komponenten eines 140Mbit/s-HDTV-Codecs14. FKTG-Jahrestagung, (74-75)
    • Pirsch, P. (1981): Adaptive Intra-Interframe DPCM CoderPicture Coding Symposium
    • Pirsch, P.; Netravali, N. (1982): Hierarchical Transmission of Multilevel Dithered ImagesInternational Conference on Electronic Image Processing, (16-21)
    • Hecht, V.; Rönner, K.; Pirsch, P. (1991): A Defect Tolerant Systolic Array Implementation for Real Time Image ProcessingProc. of Int. Conf. on Application-Specific Array Processors (ASAP), (25-39)
    • Pirsch, P. (1983): Codes mit minimaler Wahrscheinlichkeit für PufferspeicherüberlaufNTG-Fachbericht 84, (219-225)
    • Hecht, V.; Rönner, K.; Pirsch, P. (1991): An Advanced Programmable 2D-Convolution Chip for Real Time Image ProcessingProc. of IEEE Intl. Symposium on Circuits and Systems (ISCAS), 4, (1897-1900)
    • Pirsch, P.; Bierling, M. (1983): Changing the Sampling Rate of Video Signals by Rational FactorsConference Record EUSIPCO'83, (171-174)
    • Winzker, M.; Grüger, K.; Pirsch, P. (1993): Schaltungsstrukturen für die Realisierung integrierter HDTV-TeilbandfilterGME-Fachbericht 11 Mikroelektronik, Vorträge der GME-Fachtagung, Dresden, VDE-Verlag GmbH (345-350)
    • Drews, S.; Pirsch, P.; Schaper, K. (1984): Circuit Technique for VLSI Design of a Video CodecICC'84 Conference Record, (250-255)
    • Schönfeld, J.; Pirsch, P. (1993): Single Board Image Processing Unit for Vehicle GuidanceInternational Conference on VLSI, (4.2.1-10)
    • Pirsch, P. (1985): Coding of TV signals for broadband communicationsConference Record TV Symposium, (599-609)
    • Schönfeld, J.; Pirsch, P. (1993): Image Processing Board for Real-Time Extraction of Line Symbols from Video SequencesVLSI Signal Processing VI, L. D. J. Eggermont, P. Dewilde, E. Deprettere, J. van Meerbergen, IEEE (30-38)
    • Pirsch, P. (1986): Architektur und Schaltkreistechnik von CMOS ICs für die Codierung von VideosignalenNTG-Fachbericht Mikroelektronik für die Informationstechnik, (213-222)
    • Schönfeld, J.; Pirsch, P. (1993): Compact Hardware Realization for Hough Based Extraction of Line Segments in Image Sequences for Vehicle GuidanceICASSP, (I-397-401)
    • Pirsch, P. (1987): Systemarchitektur - Strategien für die schnelle digitale SignalverarbeitungTagungsband der Professorenkonferenz 1987 der DBP, (137-148)
    • Hoffer, R.; Gehrke, W.; Pirsch, P. (1993): Heterogenous multiprocessor architecture for video coding applicationsVideo Communications and PACS for Medical Applications, Proc. of SPIE, 1977, (417-424)
    • Pirsch, P. (1987): VLSI DPCM Codecs for Video Signal CodingPicture Coding Symposium
    • Pirsch, P.; Gehrke, W.; Hoffer, R. (1993): A Hierarchical Multiprocessor Architecture for Video Coding ApplicationsInternational Symposium on Circuits and Systems, (1759-1753)
    • Pirsch, P.; Micke, T.; Bao, H. (1987): Digital Filters for Video Codecs with Oversampled ADC and DACInternational Symposium on Circuits and Systems, (217-220)
    • Pirsch, P.; Gehrke, W.; Hoffer, R. (1993): Parallel VLSI Implementation of Video Coding AlgorithmsIEEE Workshop on Visual Signal Processing and Communications, (335-338)
    • Komarek, T.; Pirsch, P. (1989): VLSI Architectures for Hierarchical Block Matching AlgorithmsIFIP Workshop on Parallel Architectures on Silicon, (168-181)
    • Gehrke, W.; Hoffer, R.; Pirsch, P. (1993): Hierarchische Multiprozessorarchitekturen für die Echtzeitvideocodierung5. Dortmunder Fernsehseminar, (188-195)
    • Langemeyer, S.; Kloos, H.; Simon-Klar, C.; Friebe, L.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2003): A Compact and Flexible Multi-DSP System for Real-Time SAR ApplicationsProceedings IGARSS2003, IEEE (CD-ROM)
      ISBN: 0780379306
    • Gaedke, K.; Franzen, J.; Pirsch, P. (1993): A Fault-Tolerant DCT-Architecture based on Distributed ArithmeticIEEE International Symposium on Circuits and Systems, (1583-1586)
    • Berekovic, M.; Stolberg, -.; Flügel, S.; Moch, S.; Kulaczewski, B.; Friebe, L.; Hilgenstock, J.; Mao, X.; Klussmann, H.; Pirsch, P. (2002): Implementing The MPEG-4 AS Profile on a Multi-Core System on Chip ArchitectureProceedings of 3rd Workshop and Exhibition on MPEG-4 (WEMP4), IEEE, MPEG-4 Industry Forum (M4IF)
    • Jachalsky, J.; Wahle, M.; Pirsch, P.; Gehrke, W. (2002): A Flexible, Fully Configurable Architecture for MPEG-2 Video EncodingProceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), IEEE Press, Piscataway, NJ (1063-1066)
      ISBN: 0780375963
    • Grüger, K.; Winzker, M.; Gehrke, W.; Pirsch, P. (1992): VLSI Realization of 2D HDTV Subband Filterbanks with On-Chip Line Memories and FIFOsProc. of ESSCIRC '92, 18th European Solid State Circuits Conference, (319-322)
    • Stolberg, -.; Berekovic, M.; Pirsch, P. (2002): A Platform-Independent Methodology for Performance Estimation of Streaming Media ApplicationsProceedings 2002 IEEE International Conference on Multimedia and EXPO (ICME2002), IEEE Press, Piscataway, NJ (CD-ROM)
      ISBN: 0780373057
    • Langerwerf, M.; Reuter, C.; Kropp, H.; Pirsch, P. (2002): Benefits of Macro-based Multi-FPGA Partitioning for Video Processing Applications13th IEEE International Workshop on Rapid System Prototyping, IEEE Computer Society, Los Alamitos CA (60-65)
      DOI: 10.1109/IWRSP.2002.1029739
      ISBN: 076951703X
    • Wilberg, J.; Schöbinger, M.; Pirsch, P. (1992): Hierarchical Multiprocessor System for Video Signal ProcessingProc. of SPIE Visual Communications and Image Processing, 1818, (1076-1087)
    • Simon-Klar, C.; Friebe, L.; Kloos, H.; Lieske, H.; Hinrichs, W.; Pirsch, P. (2002): A Multi DSP Board for Real Time SAR Processing using the HiPAR-DSP 16Proceedings of the International Geoscience and Remote Sensing Symposium 2002, IEEE International (2750-2752)
      ISBN: 0780375360
    • Winzker, M.; Grüger, K.; Pirsch, P. (1992): VLSI Architecture of Filterbanks for an HDTV Subband Coder with 140 Mbit/sForth Int. Workshop on HDTV and beyond, Elsevier (165-172)
    • Jachalsky, J.; Pirsch, P. (2002): ChipDesign - A Novel Approach to Project-Oriented CoursesProceedings of the 4th European Workshop on Microelectronics Education (EWME 2002), Marcombo de Boixareu Editores, Barcelona (241-243)
      ISBN: 8426713254
    • Winzker, M.; Grüger, K.; Gehrke, W.; Pirsch, P. (1992): Architecture and Realization of HDTV Subband FiltersIEEE workshop on Visual Signal Processing and Communications, Raleigh, NC, S. A. Rajala, K. H. Tzou, IEEE (21-24)
    • Schönfeld, M.; Schwiegershausen, M.; Pirsch, P. (1992): Synthese von Registerschaltungen für den Datentransfer mit systolischen ArraysITG-Fachbericht 122: Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, VDE-Verlag GmbH (147-156)
    • Berekovic, M.; Stolberg, -.; Pirsch, P. (2001): Implementing the MPEG-4 AS Profile for Streaming Video on a SOC Multimedia ProcessorProceedings of the 3rd Workshop on Media and Streaming Processors (MSP-3), Keiner (39-44)
      ISBN: Keine
    • Pirsch, P. (1992): VLSI Architectures and Implementations for Video and HDTVConference on Video/HDTV Signal Processing, University of California, Santa Barbara
    • Kloos, H.; Friebe, L.; Simon-Klar, C.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2002): HiPAR-DSP 16 for the Development of a Scalable Real- Time SAR ProcessorEUSAR 2002, VDE, Berlin (425-428)
      ISBN: 3-8007-2697-1
    • Pirsch, P. (1992): VLSI Architectures for Digital Video CodingIEEE Workshop on Visual Signal Processing and Communications, S. A. Rajala, K. H. Tzou, IEEE (1-8)
    • Pirsch, P.; Grüger, K.; Winzker, M. (1992): VLSI Architectures of Two-Dimensional Filters for HDTV CodingProc. of IEEE Int. Symposium on Circuits and Systems (ISCAS), 4, IEEE (1648-1651)
    • Friebe, L.; Stolberg, -.; Berekovic, M.; Moch, S.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A System-on-Chip Architecture with Two Multimedia DSPs and a RISC CoreIEEE International SOC Conference, IEEE, Piscataway, NJ (85-88)
      ISBN: 0780381823
    • Jeschke, H.; Gaedke, K.; Pirsch, P. (1992): A VLSI Based Multiprocessor Architecture for Video Signal ProcessingProc. of IEEE Int. Symposium on Circuits and Systems (ISCAS), (1685-1688)
    • Stolberg, -.; Berekovic, M.; Friebe, L.; Moch, S.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal ProcessingProceedings 2003 IEEE Workshop on Signal Processing Systems, IEEE, Piscataway, NJ (189-194)
      ISBN: 0780377958
    • Schwiegershausen, M.; Schönfeld, M.; Pirsch, P. (1994): Abbildung komplexer Bildverarbeitungsverfahren auf heterogene MultiprozessorsystemeRechnergestützter Entwurf und Architektur mikroelektronischer Systeme, Vorträge der 3. GI/ITG/GME-Fachtagung Oberwiesenthal, D. Monjau, (106-115)
    • Reuter, C.; Martín, J.; Stolberg, -.; Pirsch, P. (2003): Performance Estimation of Streaming Media Applications for Reconfigurable PlatformsInternational Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS Initiative, Leiden (Die Niederlanden) (42-45)
      ISBN: 9080795712
    • Berekovic, M.; Flügel, S.; Stolberg, -.; Friebe, L.; Moch, S.; Kulaczewski, B.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core Architecture for Image and Video ApplicationsProceedings ICIP2003, IEEE, Piscataway, NJ (101-104)
      ISBN: 0780377508
    • Jachalsky, J.; Wahle, M.; Pirsch, P.; Capperon, S.; Gehrke, W.; Kruijtzer, M.; Nuñez, A. (2003): A Core for Ambient and Mobile Intelligent Imaging ApplicationsProceedings of the 2003 IEEE International Conference on Multimedia & Expo (ICME 2003), IEEE Press, Piscataway, NJ (CDROM)
      ISBN: 0780379667
    • Pirsch, P.; Berekovic, M.; Stolberg, -.; Jachalsky, J. (2003): VLSI Architectures for MPEG-4Proc. 2003 International Symposium on VLSI Technology, Systems, and Applications, IEEE Press, Piscataway, NJ (208-212)
      ISBN: 0780377656
    • Stolberg, -.; Berekovic, M.; Friebe, L.; Moch, S.; Flügel, S.; Mao, X.; Kulaczewski, B.; Klußmann, H.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing ApplicationsProceedings Design, Automation and Test in Europe (DATE2003) - Designer's Forum, IEEE, Piscataway, NJ (8-13)
      ISBN: 0769518702
    • Cholewa, F.; Pfitzner, M.; Fahnemann, C.; Pirsch, P.; Blume, H. (2014): Synthetic Aperture Radar with Backprojection: A Scalable, Platform Independent Architecture for Exhaustive FPGA Resource UtilizationInternational Radar Conference 2014 (RADAR)
    • Wielage, M.; Cholewa, F.;Pirsch, P.;Blume, H. (2016): Experimental violation of the Start-Stop-Approximation using a Holistic Rail-based UWB FMCW-SAR System11th European Conference on Synthetic Aperture Radar (EUSAR 2016)
    • Cholewa, F.: Wielage, M.; Pirsch, P.; Blume, H. (2016): An FPGA Architecture for Velocity Independent Backprojection in FMCW-based SAR SystemsThe 16th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT2016)
    • Wielage, M.; Cholewa, F.; Riggers, C.; Pirsch, P.; Blume, H. (2017): Parallelization Strategies for Fast Factorized Backprojection SAR on Embedded Multi-Core Architectures2017 IEEE International Conference on Microwave, Communications, Antennas and Electronic Systems
    • Cholewa, F.; Wielage M.; Pirsch, P.; Blume, H. (2017): Synthetic Aperture Radar with Fast Factorized Backprojection: A Scalable, Platform Independent Architecture for Exhaustive FPGA Resource UtilizationInternational Conference on Radar Systems 2017 (RADAR)
    • Wielage, M.; Cholewa, F.; Fahnemann, C.; Pirsch, P.; Blume, H. (2017): High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized BackprojectionProceedings of CANDAR Symposium (2017)

    Journalbeiträge

    • Berekovic, M.; Pirsch, P.; Kneip, J. (1998): An Algorithm-Hardware-System Approach to VLIW Multimedia ProcessorsJournal of VLSI Signal Processing Systems, 20(1-2), (163-180)
    • Pirsch, P.; Stolberg, -. (1998): VLSI Implementations of Image and Video Multimedia Processing SystemsIEEE Transactions on Circuits and Systems for Video Technology, 8(7), (878-891)
    • Berekovic, M.; Kloos, H.; Pirsch, P. (1999): Hardware Realization of a Java Virtual Machine for High Performance Multimedia ApplicationsJournal of VLSI Signal Processing Systems, 22(1), (31-44)
    • Berekovic, M.; Pirsch, P.; Selinger, T.; Miro, C.; Lafage, A.; Wels, -.; Heer, C.; Ghigo, G. (2002): Architecture of an Image Rendering Co-Processor for MPEG-4 Visual CompositingKluwer Journal of VLSI Signal Processing Systems, 31(2), Kluwer Academic Publishers (157-171)
      ISBN: 09225773
    • Berekovic, M.; Stolberg, J.; Kulaczewski, B.; Pirsch, P.; Möller, H.; Runge, H.; Kneip, J.; Stabernack, B. (1999): Instruction Set Extensions for MPEG-4 VideoJournal of VLSI Signal Processing Systems, 23(1), (27-50)
    • Reuter, C.; Kropp, H.; Pirsch, P. (2000): Rapid Prototyping von Videosignalverarbeitungsverfahrenit+ti Informationstechnik und Technische Informatik, 42(3), Oldenbourg Verlag (5-9)
      ISBN: 0944-2774
    • Kneip, J.; Ohmacht, M.; Rönner, K.; Pirsch, P. (1995): Architecture and C++-Programming Environment of a Highly Parallel Image Signal ProcessorMicroprocessing and Microprogramming, 41(5-6), (391-408)
    • Jeschke, H.; Gaedke, K.; Pirsch, P. (1992): Multiprocessor Performance for Real-Time Processing of Video Coding ApplicationsIEEE Transactions on Circuits and Systems for Video Technology, Special Issue On: VLSI Circuits And Systems for Video Applications, 2(2), (221-230)
    • Hecht, V.; Rönner, K.; Pirsch, P. (1993): A Defect Tolerant Systolic Array Implementation for Real Time Image ProcessingJournal of VLSI Signal Processing, 5(1), (37-47)
    • Musmann, G.; Pirsch, P. (1993): Coding Algorithms and VLSI Implementations for Digital TV and HDTV Satellite BroadcastEuropean Transactions on Telecommunications and Related Technologies, 4(1)
    • Gaedke, K.; Jeschke, H.; Pirsch, P. (1993): A VLSI Based MIMD Architecture of a Multiprocessor System for Real-Time Video Processing ApplicationsJournal of VLSI Signal Processing, 5(2/3), (159-169)
    • Winzker, M.; Grüger, K.; Gehrke, W.; Pirsch, P. (1993): VLSI Chip Set for 2D HDTV Subband Filtering with On-Chip Line MemoriesIEEE Journal of Solid State Circuits, 28(12), (1354-1361)
    • Winzker, M.; Pirsch, P. (1994): Reduktion des Schaltfaktors durch das Ausnutzen statistischer Eigenschaften von VideosignalenMikroelektronik, 8(5), (228-291)
    • Pirsch, P.; Demassieux, N.; Gehrke, W. (1995): VLSI Architectures for Video Compression - A SurveyProceedings of the IEEE, 83(2), (220-246)
    • Langemeyer, S.; Pirsch, P.; Blume, H. (2012): Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without TransposeInternational Journal of Parallel Programming, Springer (1-24)
      DOI: 10.1007/s10766-012-0225-6
      ISBN: 0885-7458
    • Banz, C.; Hesselbarth, S.; Flatt, H.; Blume, H.; Pirsch, P. (2011): Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-ImplementationTransactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), Springer
    • Pirsch, P.; Netravali, N. (1983): Transmission of Gray Level Images by Multilevel Dither TechniquesComputer & Graphics, 7(2), (31-44)
    • Pirsch, P. (1984): Quellencodierung von BildsignalenNTZ, 37/38(1-12/1-3), Arbeitsblattserie
    • Pirsch, P. (1984): Video Codec for Broadband CommunicationsElectrical Communication, 58(4), (447-449)
    • Pirsch, P. (1985): Design of a DPCM Codec for VLSI Realization in CMOS TechnologyProceedings of the IEEE, 73(4), (592-598)
    • Musmann, G.; Pirsch, P.; Grallert, J. (1985): Advances in Picture CodingProceedings of the IEEE, 73(4), (523-548)
    • Bostelmann, G.; Pirsch, P. (1985): Coding of Video SignalsElectrical Communications, 59(3), (286-294)
    • Komarek, T.; Pirsch, P. (1989): Array Architektures for Block Matching AlgorithmsIEEE Trans. on Circuits and Systems, 36(10), (1301-1308)
    • Pirsch, P.; Grüger, K. (1990): Realisierungsaspekte beim zukünftigen hochauflösenden FernsehenMikroelektronik, 4(2), (74-75)
    • Pirsch, P.; Speidel, J. (1991): Die Bedeutung der Mikroelektronik für die BildcodierungMikroelektronik, 5(3), VDE-Verlag (110)
    • Pirsch, P. (1982): Adaptive Intra/Interframe PredictionBell System Techn. Journal, 61(5), (747-764)
    • Pirsch, P. (1982): Stability Conditions of DPCM CodersIEEE Trans. on Communications, COM-30, (1174-1184)
    • Pirsch, P.; Stenger, L. (1976): Statistical Analysis and Coding of Color Video SignalsActa Electronica, 19(4), (277-287)
    • Pirsch, P. (1981): Design of DPCM Quantizers for Video Signals Using Subjective TestsIEEE Trans. on Communications, COM-29, (990-1000)
    • Pirsch, P.; Dehnhardt, A.; Flatt, H.; Flügel, S. (2006): Hardware-Realisierungen komplexer Bild- und VideosignalverarbeitungTele Kommunikation Aktuell, 60. Jahrgang, Heft 07-12, Juli-Dezember 2006
    • Stolberg, -.; Berekovic, M.; Moch, S.; Friebe, L.; Kulaczewski, B.; Flügel, S.; Klußmann, H.; Dehnhardt, A.; Pirsch, P. (2005): HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal ProcessingJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 41(1), Springer Science+Business Media (9-20)
      ISBN: 09225773
    • Stolberg, -.; Berekovic, M.; Pirsch, P. (2005): A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing ApplicationsJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 41(2), Springer Science+Business Media B.V., New York (139-151)
      ISBN: 09225773
    • Berekovic, M.; Moch, S.; Pirsch, P. (2004): A scalable, clustered SMT processor for digital signal processingACM SIGARCH Computer Architecture News, 32(3), ACM Press New York, NY, USA (62-69)
      ISBN: 01635964
    • Moch, S.; Berekovic, M.; Stolberg, -.; Friebe, L.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2004): HiBRID-SoC: A Multi-Core Architecture for Image and Video ApplicationsACM SIGARCH Computer Architecture News, 32(3), ACM Press New York, NY, USA (55-61)
      ISBN: 01635964
    • Payá-Vayá, G.; Martín-Langerwerf, J.; Pirsch, P. (2010): A Multi-Shared Register File Structure for VLIW ProcessorsJournal of Signal Processing Systems, 58(2), Springer New York (215-231)
      DOI: 10.1007/s11265-009-0355-2
      ISBN: 1939-8018 (Print) 1939-8115 (Online)
    • Flatt, H.; Tarnowsky, A.; Blume, H.; Pirsch, P. (2010): Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-ArchitekturAdvances in Radio Science, 8, (135-142)
      DOI: 10.5194/ars-8-135-2010
    • Pirsch, P. (2006): Seiner Zeit voraus gedachtUni Magazin Hannover, Leibniz, Auf den Spuren des großen Denkers, 3-4, Leibniz Universität Hannover, (36-39)
    • Pirsch, P.; Reuter, C.; Wittenburg, P.; Kulaczewski, B.; Stolberg, -. (2001): Architecture Concepts for Multimedia Signal ProcessingJournal of VLSI Signal Processing Systems, 29(3), Kluwer Academic Publishers, Boston, USA (157-165)
      ISBN: 09225773
    • Hinrichs, W.; Wittenburg, P.; Lieske, H.; Kloos, H.; Ohmacht, M.; Pirsch, P. (2000): A 1.3 GOPS Parallel DSP for High Performance Image Processing ApplicationsIEEE Journal of Solid-State Circuits, 35(7), IEEE Press, Piscataway, NJ (946-952)
      ISBN: 00189200
    • Berekovic, M.; Stolberg, -.; Pirsch, P. (2002): Multi-Core System-On-Chip Architecture for MPEG-4 Streaming VideoTransactions on Circuits and Systems for Video Technology (CSVT), 12(8), IEEE Periodicals / Transactions/Journals Department (688-699)
      ISBN: 10518215
    • Grüger, K.; Pirsch, P.; Winzker, M. (1991): VLSI Architectures of Filterbanks for Subband Coding of HDTV SignalsAnnales des Télécommunications, Special Issue VLSI Architectures for Signal Processing, 46(1-2), (110-120)
    • Schönfeld, M.; Franzen, J.; Schwiegershausen, M.; Pirsch, P.; Vehlies, U.; Münzner, A. (1995): The LISA Design Environment for the Synthesis of Array Processors Including Memories for the Data Transfer and Fault Tolerance by Reconfiguration and Coding TechniquesJournal of VLSI Signal Processing, 11(1/2), (51-74)
    • Kneip, J.; Berekovic, M.; Wittenburg, P.; Hinrichs, W.; Pirsch, P. (1997): An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal ProcessorJournal of VLSI Signal Processing, 16(1), (31-40)
    • Pirsch, P.; Stolberg, J.; Chen, K.; Kung, Y. (1997): The Past, Present, and Future of Multimedia Signal ProcessingIEEE Signal Processing Magazine, 14(4), T. Chen, A. Kattsaggelos, S. Y. Kung, (48-51)

    Buchbeiträge

    • Pirsch, P. (1980): BildcodierungErfassung und Maschinelle Verarbeitung von Bilddaten, H. Kazmierczak, Springer (85-112)
    • Pirsch, P. (1987): VLSI Design of DPCM Codecs for Video SignalsVisual Communication Systems, A. N. Netravali, B. Prasada, IEEE PRESS (216-227)
    • Pirsch, P.; Freimann, A.; Klar, C.; Wittenburg, P. (2002): Processor Architectures for Multimedia ApplicationsEmbedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, Ed F. Deprettere, Jürgen Teich, and Stamatis Vassiliadis, Springer Verlag, Heidelberg (188-206)
      ISBN: 3540433228
    • Schwiegershausen, M.; Schönfeld, M.; Pirsch, P. (1995): Mapping complex Image Processing Algorithms onto Heterogenous Multiprocessors regarding Architecture dependent Performance ParametersAlgorithms and Parallel VLSI Architectures III, M. Moonen, F. Catthoor, Elsevier (353-364)
    • Rönner, K.; Kneip, J.; Pirsch, P. (1995): A Highly Parallel Single-Chip Video Signal ProcessorAlgorithms and Parallel VLSI Architectures III, M. Moonen, F. Catthoor, Elsevier Science B.V. (179-190)
    • Pirsch, P. (1995): VLSI for Video CodingHandbook of Visual Communications, H. M. Hang, J. W. Woods, Academic Press (465-500)
    • Pirsch, P.; Berekovic, M.; Freimann, A.; Stolberg, J. (1997): Video Compression ArchitecturesCircuits and Systems in the Information Age, Y. F. Huang, C. H. Wei, IEEE Short Courses at ISCAS 1997 (31-50)
    • Pirsch, P.; Gehrke, W. (1998): VLSI Architectures for Image CommunicationsThe Digital Signal Processing Handbook, V. K. Madisetti, D. B. Williams, IEEE Press (59/1-59/21)
    • Pirsch, P.; Stolberg, -. (1999): Video Signal ProcessingWiley Encyclopedia of Electrical and Electronics Engineering, 23, J. G. Webster, John Wiley & Sons, Inc. (193-205)
    • Schwiegershausen, M.; Pirsch, P. (1995): Optimization of Heterogeneous Multiprocessors for Complex Image Processing ApplicationsLogic and Architecture Synthesis - State-of-the-art and novel approaches, G. Saucier, A. Mignotte, Chapman & Hall (367-373)
    • Pirsch, P.; Grüger, K. (1994): VLSI Architectures and Circuits for Digital Coding of High Definition TelevisionDesign of VLSI Circuits for Telecommunications and Signal Processing, J. Franca, Y. Tsividis, Prentice Hall (495-527)
    • Pirsch, P.; Komarek, T. (1989): Systolic Arrays for Block Matching AlgorithmsHigh Precision Navigation, K. Linkwitz, U. Hangleiter, Springer Verlag (354-365)
    • Banz, C.; Blume, H.; Pirsch, P. (2012): Architectures for Stereo VisionSpringer Handbook on Signal Processing Systems, 2nd Edition (with the editors, scheduled 2012), S. Bhattacharyya, E. Deprettere, R. Leupers, J. Takala, Springer
    • Musmann, G.; Pirsch, P.; Grallert, J. (1989): Advances in Picture CodingVisual Communications Systems, A. N. Netravali, B. Prasada, IEEE Press (67-92)
    • Grüger, K.; Pirsch, P. (1990): Architecture of a 560 Mbit/s DPCM-HDTV-CodecSignal Proc. of HDTV, II, L. Chiariglione, Elsevier (295-303)
    • Schönfeld, J.; Pirsch, P. (1991): VLSI Implementation for Real Time Processing of Straight Line ExtractionFrom Pixels to Features II, H. Burkhardt, J. C. Simon, Elsevier (201-211)
    • Schönfeld, M.; Schwiegershausen, M.; Pirsch, P. (1992): Synthesis of intermediate memories for the data supply to processor arraysAlgorithms and Parallel VLSI Architectures II, P. Quinton, Y. Robert, Elsevier (365-370)
    • Pirsch, P. (1992): VLSI Architectures for Digital Video Signal ProcessingComputer Systems and Software Engineering, State-of-the-art, P. Dewilde, J. Vandewalle, Kluwer Academic Publ. (65-99)
    • Pirsch, P. (1993): VLSI Implementation StrategiesVLSI Implementations for Image Communications, Series Advances in Image Communications, 2, P. Pirsch, Elsevier (49-68)
    • Grüger, K.; Pirsch, P. (1993): DPCM-CodecsVLSI Implementations for Image Communications, Series Advances in Image Communications, 2, P. Pirsch, Elsevier (311-344)
    • Pirsch, P.; Wehberg, T. (1994): VLSI Architectures and Circuits for Visual CommunicationsDesign of VLSI Circuits for Telecommunications and Signal Processing, J. E. Franca, Y. Tsividis, Prentice-Hall (429-461)
    • Flatt, H.; Hesselbarth, S.; Flügel, S.; Pirsch, P. (2007): A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal ProcessingInternational Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS, Lecture Notes in Computer Science, Embedded Computer Systems: Architectures, Modeling, and Simulation(4599/2007), S. Vassiliadis, M. Berekovic, and T.D. Hämäläinen, Springer, Heidelberg (241-250)
      DOI: 10.1007/978-3-540-73625-7
      ISBN: 9783540736257
    • Septinus, K.; Grimm, C.; Rumyantsev, V.; Pirsch, P. (2008): On the Benefit of Caching Traffic Flow Data in the Link BufferEmbedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008, 8th International Workshop, Berekovic, Mladen; Dimopoulos, Nikitas; Wong, Stephan, Springer-Verlag Berlin Heidelberg (2-11)
      ISBN: 978-3-540-70549-9
    • Payá-Vayá, G.; Langerwerf, M.; Pirsch, P. (2005): RAPANUI: Rapid Prototyping for Media Processor Architecture ExplorationSAMOS V Workshop 2005, Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, et al., Springer, Berlin Heidelberg (32-40)
      DOI: 10.1007/11512622_5
      ISBN: 354026969X
    • Reuter, C.; Langerwerf, M.; Stolberg, -.; Pirsch, P. (2004): Performance Estimation of Streaming Media Applications for Reconfigurable PlatformsComputer Systems: Architectures, Modeling, and Simulation, A. Pimentel, S. Vassiliadis, Springer Verlag Berlin Heidelberg (69-77)
      DOI: 10.1007/b98714
      ISBN: 978-3-540-22377-1

    Bücher

    • Barke, E.; Soudris, D.; Pirsch, P. (Ed.) (2000): Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation (PATMOS 2000: Proceedings 10th International Workshop)Springer Verlag, Heidelberg
    • Pirsch, P. (1979): Optimierung von Farbfernseh-DPCM-Systemen unter Berücksichtigung der Wahrnehmbarkeit von QuantisierungsfehlernDissertation, University of Hannover
    • Pirsch, P. (1993): VLSI Implementations for Image CommunicationsElsevier Science Publisher
    • Pirsch, P. (1996): Architekturen der digitalen SignalverarbeitungTeubner
    • Ibrahim, K.; Pirsch, P.; McCanny, J. (Ed.) (1997): Signal Processing Systems (SIPS 97)IEEE Press
    • Pirsch, P. (1998): Architectures for Digital Signal ProcessingJohn Wiley & Sons, Inc.
  • Forschungsprojekte

    Entwurfsraumexploration

    • Miniaturisierter Echtzeit SAR Prozessor
      Das Ziel dieses Projektes ist die echtzeitfähige Generierung und Kompression hochauflösender Luftbilder nach dem Prinzip des Synthetic Aperture Radar. Das SAR gehört zu der Klasse der abbildenden Radarsysteme und bietet gegenüber kamerabasierten elektro-optischen Sensoren eine von Witterung und Tageslicht annähernd unabhängige Einsatzfähigkeit. Moderne Sensoren erreichen hierbei Auflösungen von weniger als 10 cm bei Flughöhen von 10 km. Durch den Einsatz moderner FPGAs wird eine schritthaltende Bilddatengenerierung an Bord der Sensorplattform auch bei sehr großen Bilddimensionen ermöglicht.
      Leitung: Prof. Dr.-Ing. H. Blume
      Team: F. Cholewa, C. Fahnemann, N. Rother
      Jahr: 2020
      Laufzeit: 2008-2020