Leaders:  Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá
Team:  Dipl.-Ing. Nico Mentzer
Year:  2014
Date:  01-05-10
Sponsors:  Bundesministerium für Bildung und Forschung (BMBF)
Lifespan:  Mai 2010 - April 2013
Is Finished:  yes

Project goal

The goal of this sub-project of the BMBF project "Automatic Situation Interpretation for Event Triggered Video Surveillance" is to elaborate a concept for a hardware architecture that enables a SIFT (Scale Invariant Feature Transform) feature extraction under application-specific processing conditions as performance and power consumption. SIFT features offer a good basis for robust object identification and tracking for event triggered video surveillance. The field of application is thereby the airport apron, which is highly relevant to security. The concept was implemented on a FPGA-based hardware platform to build a demonstrator which was tested at the end of the project at the airport of Braunschweig.


An object detection based on SIFT features has the advantage that objects can be detected regardless of their scale and rotation in the image.  The downside is however the high workload introduced by the feature extraction. This prevents real-time processing especially in current embedded systems in smart camera. Even with an optimized CPU implementation, processing of a single frame of the input video stream still requires over a second for SIFT-based object detection. Moreover, with a power dissipation of about 200 W wdisqualifies GPUs for the usage in an embedded system.

Contribution of IMS

In this sub-project of the BMBF project, the IMS work group will elaborate a concept for an hardware architecture that enables SIFT-based object detection. The hardware architecture consists of an application-specific instruction-set processor (ASIPs) and will be used to implement a novel robust security system based on SIFT features during the ASEV project.

The functionality of this novel system was tested in a real-world environment at the airport of Braunschweig. Therefore, the hardware architecture will be mapped on a FPGA-base hardware platform. FPGAs thereby offer the flexibility that is needed during system design when considering diverse implementation options.

As a final step, the implementation costs of the hardware architecture as a system-on-chip have been analyzed for a state-of-the are ASIC technology. The results of this study can form the basis of a commercialization of the novel robust SIFT-based security system for video surveillance. The criteria used for this study are e. g. silicon area requirements, throughput and power dissipation.