Miniaturisierter Echtzeit SAR Prozessor

Compact Realtime SAR-Image processor

Leaders:  Prof. Dr.-Ing. H. Blume
Team:  F. Cholewa, C. Fahnemann, N. Rother
Year:  2020
Lifespan:  2008-2020

Synthetic Aperture Radar (SAR)

Airborne and spaceborne surveillance is used in several fields of application such as: 

  • Disaster control
  • Digital carthography
  • Generation of digital elevation maps

Both electro-optic and radar based sensors are used in these fields of application. The inherent advantage of optical sensors is the direct image mapping of observed areas while signal processing demands are relatively low.

Compared to optical systems, radar based sensors operate independent of daylight and weather conditions by active transmission and reception of electromagnietic waves. Characteristic reflections of specific materials vary with the carrier frequency of the radar. Synthetic Aperture Radar (SAR) takes advantage of the Doppler-Effect which occurs because of relative movement between sensor carrier and illuminated area creating high resolution aerial images at moderate antenna size. Besides satellites and aircrafts, small unmanned aerial vehicles (UAVs) play a major role in future applications because of their significant advantages such as moderate system costs, high flexibility and utilizability. 

Generation of aerial images by using SAR technology demands for very high performance digital signal processors. First, because of the underlying algorithm complexity, second because of high data rates of state-of-the-art SAR sensor systems (~Gbit/s).

These restrictions increase by means of strictly limited form factor and power consumption (max. ~30W) for UAVs.

SAR-Processor (HiPAR-DSP)

A real-time SAR processor, which can be used onboard UAVs has been developed at the LfI. Due to possible platform crashes, onboard storage of SAR sensor rawdata is prohibited for UAVs. Therefore, sensor data has to be trasmitted to a ground station over radio links during data aquisition. Disadvantageous statistical characteristics of SAR sensor rawdata prevent efficient compression techniques. In contrast, onboard real-time processing of aerial images enable for usage of optical compression techniques.

As a first step, real-time processing has been implemented on a compact double-eurocard printed circuit board. SAR processing algorithms are mapped on a specialized signal processor (HiPAR-DSP) which has been developed at the Institut of Mikroelectronic Systemes (IMS), University of Hannover. Because of multiple parallel data paths (SIMD), all relevant processing steps like FFTs and FIR operations can be implemented at very high efficiency.

SAR-Processor and Image Coder (HiBRID-SoC)

In a second step, image compression has been applied at an increased level of resolution. A combined integraton of SAR processing algorithms and image compression techniques is achieved by using the HiBRIDSoC, which has also been developed at the Institut of Mikroelectronic Systemes (IMS). This System-On-Chip architecture uses multiple processor cores for enahances processing performance. Besides the HiPAR core, a specialized macro block processor core has been integrated on the SoC. This enables for block based compression methods e.g. JPEG. Therefore, the overall processing chain has successfully been implemented on a single DSP.

RISC/FPGA based real-time SAR image generation onboard UAVs


Continuous improvements in the field of SAR sensor systems as well as focussing algorithms demand for higher computational power. Furthermore, flexibility in terms of algorithm mapping has become a major issue in current research. Because of the restrictive constraints of small UAVs, a compact RISC/FPGA platform has been developed which is suitable for real-time image generation at highest resolutions. By using a programmable RISC processor and a reconfigurable FPGA, efficient mapping of state-of-the-art SAR focussing algorithms at data rates > 300Mbit/s is achieved while the overall power consumption does not exceed more than 15W.

Contact: Martin Pfitzner, Fabian Cholewa, Matthis Wielage