Institute
Holger Blume

Prof. Dr.-Ing. Holger Blume

Prof. Dr.-Ing. Holger Blume
Address
Appelstr. 4
30167 Hannover
Prof. Dr.-Ing. Holger Blume
Address
Appelstr. 4
30167 Hannover

CAREER

Holger Blume, born in 1967, studied electrical engineering at the University of Dortmund from 1987 to 1992. During his studies he was a scholarship holder of the German National Academic Foundation. From 1993 to 1996 he was a research assistant in the Circuits for Information Processing group at the University of Dortmund (Prof. Dr. H. Schröder). From 1996-1998 he was employed as a research associate at the Informatik Centrum Dortmund (ICD). In 1997, he received his PhD with honors from the University of Dortmund on the topic of "Nonlinear Fault-Tolerant Interpolation of Intermediate Images".

From 1998 to 2008, he worked first as a senior engineer and later as an academic senior councillor at the Department of General Electrical Engineering and Data Processing Systems at RWTH Aachen University (Prof. Dr. T. G. Noll). In February 2008 he habilitated there with a thesis on "Exploration of the Design Space for Heterogeneous Architectures for Digital Video Signal Processing".

In July 2008, he followed a call to Leibniz Universität Hannover where he has been working since then as professor for "Architectures and Systems" and as managing director of the Institute for Microelectronic Systems (IMS).

  • Publications

    Showing entries 1 - 20 out of 314
    1 2 3 4 5 6 7 Last

    Correction to : Multicore Performance Prediction with MPET: Using Scalability Characteristics for Statistical Cross-Architecture Prediction (Journal of Signal Processing Systems, (2020), 92, 9, (981-998), 10.1007/s11265-020-01563-w). / Arndt, Oliver Jakob; Lüders, Matthias; Riggers, Christoph; Blume, Holger.

    In: Journal of Signal Processing Systems, 2021.

    Research output: Contribution to journalComment/debateResearchpeer review

    The Bose-Einstein Condensate and Cold Atom Laboratory. / Frye, Kai; Abend, Sven; Bartosch, Wolfgang; Bawamia, Ahmad; Becker, Dennis; Blume, Holger; Braxmaier, Claus; Chiow, Sheng-Wey; Efremov, Maxim A.; Ertmer, Wolfgang; Fierlinger, Peter; Franz, Tobias; Gaaloul, Naceur; Grosse, Jens; Grzeschik, Christoph; Hellmig, Ortwin; Henderson, Victoria A.; Herr, Waldemar; Israelsson, Ulf; Kohel, James; Krutzik, Markus; Kürbis, Christian; Lämmerzahl, Claus; List, Meike; Lüdtke, Daniel; Lundblad, Nathan; Marburger, J. Pierre; Meister, Matthias; Mihm, Moritz; Müller, Holger; Müntinga, Hauke; Nepal, Ayush M. ; Oberschulte, Tim; Papakonstantinou, Alexandros; Perovšek, Jaka; Peters, Achim; Prat, Arnau; Rasel, Ernst M.; Roura, Albert; Sbroscia, Matteo ; Schleich, Wolfgang P.; Schubert, Christian; Seidel, Stephan T.; Sommer, Jan; Spindeldreier, Christian; Stamper-Kurn, Dan; Stuhl, Benjamin K.; Warner, Marvin; Wendrich, Thijs; Wenzlawski, André; Wicht, Andreas; Windpassinger, Patrick; Yu, Nan; Wörner, Lisa.

    In: EPJ Quantum Technology, Vol. 8, No. 1, 1, 04.01.2021.

    Research output: Contribution to journalArticleResearchpeer review

    A Survey on Application Specific Processor Architectures for Digital Hearing Aids. / Gerlach, Lukas Konrad; Payá Vayá, Guillermo; Blume, Holger Christoph.

    In: Journal of Signal Processing Systems, 20.03.2021.

    Research output: Contribution to journalArticleResearchpeer review

    Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology. / Stuckenberg, Tobias; Rücker, Malte; Rother, Niklas; Nowosielski, Rochus; Wiese, Frank; Blume, Holger.

    Proceedings of the 2021 IEEE Nordic Circuits and Systems Conference (NORCAS). 2021.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Markerless camera-based vertical jump height measurement using openpose. / Webering, Fritz; Blume, Holger; Allaham, Issam.

    2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2021. IEEE Computer Society, 2021. p. 3863-3869 ( IEEE Computer Society Conference on Computer Vision and Pattern Recognition workshops).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Measuring vertical jump height using a smartphone camera with simultaneous gravity-based calibration. / Webering, Fritz; Seeger, Leo; Rother, Niklas; Blume, Holger Christoph.

    2021. Paper presented at IEEE International Conference on Consumer Electronics 2021.

    Research output: Contribution to conferencePaperResearchpeer review

    Multicore performance prediction with MPET : Using scalability characteristics for statistical cross-architecture prediction. / Arndt, Oliver Jakob; Lüders, Matthias; Riggers, Christoph; Blume, Holger.

    In: Journal of Signal Processing Systems, Vol. 92, No. 9, 09.2020, p. 981-998.

    Research output: Contribution to journalArticleResearchpeer review

    Psychophysics Study on LED Flicker Artefacts for Automotive Digital Mirror Replacement Systems. / Behmann, Nicolai; Blume, Holger.

    In: IS and T International Symposium on Electronic Imaging Science and Technology, Vol. 2020, No. 11, 234, 26.01.2020.

    Research output: Contribution to journalConference articleResearchpeer review

    KAVUAKA : Chip Design für digitale Hörhilfen. / Blume, Holger Christoph; Payá Vayá, Guillermo; Gerlach, Lukas Konrad.

    In: Unimagazin : Forschungsmagazin der Leibniz-Universität Hannover, Vol. 2020, No. 1, 2020, p. 18-20.

    Research output: Contribution to journalArticleResearch

    SmartHeaP - Smart Hearing Aid Processor - Ein industrielles Translationsprojekt für digitale Hörhilfen. / Blume, Holger Christoph; Payá Vayá, Guillermo; Karrenbauer, Jens Christian; Benndorf, Jens; Blawat, Meinolf.

    In: Unimagazin : Forschungsmagazin der Leibniz-Universität Hannover, 01.2020.

    Research output: Contribution to journalArticleResearch

    Issue-slot based predication encoding technique for vliw processors. / Gerlach, Lukas; Stuckmann, Fabian; Blume, Holger; Paya-Vaya, Guillermo.

    2020 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9200304.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments. / Gesper, Sven; Weissbrich, Moritz; Stuckenberg, Tobias; Jaaskelainen, Pekka; Blume, Holger; Paya-Vaya, Guillermo.

    In: International Journal of Parallel Programming, 26.12.2020.

    Research output: Contribution to journalArticleResearchpeer review

    Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing AIDS. / Karrenbauer, Jens; Gerlach, Lukas; Paya-Vaya, Guillermo; Blume, Holger.

    2020 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9200250 (2020 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Multicore Performance Prediction – Comparing Three Recent Approaches in a Case Study. / Lüders, Matthias; Arndt, Oliver Jakob; Blume, Holger.

    Euro-Par 2019: Parallel Processing Workshops - International Workshops, Revised Selected Papers. ed. / Ulrich Schwardmann; Christian Boehme; Dora B. Heras; Valeria Cardellini; Emmanuel Jeannot; Antonio Salis; Claudio Schifanella; Ravi Reddy Manumachu; Dieter Schwamborn; Laura Ricci; Oh Sangyoon; Thomas Gruber; Laura Antonelli; Stephen L. Scott. Springer Nature, 2020. p. 282-294 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 11997 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Optimized Minimum-Search for SAR Backprojection Autofocus on GPUs Using CUDA. / Rother, Niklas; Fahnemann, Christian; Wittler, Jan; Blume, Holger Christoph.

    2020 IEEE Radar Conference, RadarConf 2020. IEEE Computer Society, 2020. 9266636 (IEEE National Radar Conference - Proceedings; Vol. 2020-September).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Automated Bioreactor System for the Cultivation of Autologous Tissue-Engineered Vascular Grafts. / Stanislawski, Nils; Cholewa, Fabian; Heymann, Henrik; Kraus, Xenia; Heene, Sebastian; Witt, Martin; Thoms, Stefanie; Blume, Cornelia; Blume, Holger.

    42nd Annual International Conferences of the IEEE Engineering in Medicine and Biology Society: Enabling Innovative Technologies for Global Healthcare, EMBC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 2257-2261 9175340 (Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS; Vol. 2020-July).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    CereBridge : An Efficient, FPGA-based Real-Time Processing Platform for True Mobile Brain-Computer Interfaces. / Wahalla, Marc-Nils; Vaya, Guillermo Paya; Blume, Holger.

    42nd Annual International Conferences of the IEEE Engineering in Medicine and Biology Society: Enabling Innovative Technologies for Global Healthcare, EMBC 2020. IEEE, 2020. p. 4046-4050 9175623.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Improving the Performance of a High-Temperature DSP Using Circuit-Level Timing Speculation. / Weißbrich, Moritz; Roskamp, Steffen; Webering, Fritz; Blume, Holger; Payá-Vayá, Guillermo.

    2020. CadenceLIVE Europe 2020.

    Research output: Contribution to conferenceSlides to presentationResearch

    Portable implementationsfor heterogeneous hardwareplatforms in autonomousdriving systems. / Arndt, Oliver Jakob; Rallapalli, Parwesh; Blume, Holger Christoph.

    Big Data Analytics for Cyber-Physical Systems: Machine Learning for the Internet of Things. Elsevier, 2019. p. 113-143.

    Research output: Chapter in Book/Report/Conference proceedingContribution to book/anthologyResearch

    Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics. / Arndt, Oliver Jakob; Luders, Matthias; Blume, Holger.

    2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors (ASAP): Proceedings. Vol. 2160-052X IEEE Computer Society, 2019. p. 255-262 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer review

    Showing entries 1 - 20 out of 314
    1 2 3 4 5 6 7 Last
  • Research Projects

    Electronic Design Automation

    • GEBO - High Temperature Electronic
      In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Ing. Rochus Nowosielski
      Year: 2014
      Lifespan: 2009-20111

    Processor Architectures

    • High Temperature Measurement While Drilling
      The goal of the research is an MWD processor system for drilling tools used for geothermal drilling in ambient temperatures up to 300 °C. The processing of the project includes research aspects in the fields of hardware design, fault tolerance of digital systems and ASIC design.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Ing. Rochus Nowosielski
      Year: 2014
      Lifespan: 2012-2014
    • GEBO - High Temperature Electronic
      In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Ing. Rochus Nowosielski
      Year: 2014
      Lifespan: 2009-20111
    • RAPANUI - Rapid-Prototyping for Media Processor Architecture Exploration
      Design, implementation, and evaluation of a prototyping-based Designmethodology for processor architectures for digital signal processing.
      Leaders: Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: M. Sc. Florian Giesemann
      Year: 2014
    • OPARO
      In the development of integrated, programmable circuits, the optimization of power dissipation and temperature distribution is becoming increasingly important. So far, however, these can only be determined by very time-consuming simulations. Therefore, precise models for the determination of power dissipation shall be developed and mapped together with the functional emulation on FPGAs. By accelerating the determination of power dissipation and temperature distribution, specific optimizations of the architecture and the application code can then be made taking real input data into account.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Wirtsch.-Ing. Sebastian Hesselbarth
      Year: 2014
    • Hearing4All
      The joint venture "Hearing4all" that the IMS-AS participates in with multiple sub-projects, has been chosen as one of the federal cluster of excellence projects Friday June 15th 2012. In the scope of this project the IMS-AS aims to develop high-performance and low-power processor architectures for digital hearing systems, such as cochlear implants or hearing aids.
      Leaders: Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: M.Sc. C. Seifert, Dipl.-Ing. L. Gerlach
      Year: 2015
      Lifespan: November 2012 - December 2018
    • Stochastic Processor
      Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits.
      Leaders: Jun.-Prof. Dr.-Ing. G. Payá-Vayá, Prof. Dr.-Ing. Holger Blume
      Team: M.Sc. Moritz Weißbrich
      Year: 2015
      Sponsors: Deutsche Forschungsgemeinschaft (DFG)
      Lifespan: February 2016 - January 2019
    • TETRACOM
      Nowadays, continuous development of digital signal processing applications, e.g., video-based advanced driver assistance systems, are pushing the limits of existing embedded systems and are forcing system developers to spend more time on code optimization. These applications often involve complex mathematical functions like trigonometric, logarithmic, exponential, or square root operations. In particular, these functions can only efficiently be computed on standard general purpose embedded processors, using highly optimized, processor specific arithmetic evaluation software libraries. Another alternative is to extend the embedded processor architectures with a specific hardware accelerator.
      Leaders: Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: Dipl.-Ing. S. Nolting, Dipl.-Ing. L. Gerlach
      Year: 2016
      Lifespan: January 2016 - July 2016
    • Smart Hearing Aid Processor (Smart HeaP)
      In the Smart Hearing Aid Processor (Smart HeaP) project, a novel hearing aid processor is designed, developed and built which, despite its simple programmability and wireless Bluetooth interface, is characterized by low power consumption and high computing power.
      Leaders: Prof. Dr.-Ing. H. Blume, apl. Prof. Dr.-Ing. G. Payá Vayá
      Team: Dipl.-Ing. L. Gerlach, M.Sc. J. Karrenbauer
      Year: 2018
      Sponsors: BMBF
      Lifespan: April 2018 - April 2021
    • Multi-Energy Harvesting (MEH) - A Flexible Platform for Energy Harvesting in Home Automation
      In this project, a platform concept for intelligent home automation components is developed, which can serve as a basis for next-generation sensors and actors. The main characteristic of this platform concept is ultra-low power consumption and ultra-low voltage operation. In combination with harvested energy from multiple sources (multi-energy harvesting), an extended lifetime and reduced battery cell requirements become possible compared to current systems.
      Leaders: Prof. Dr.-Ing. H. Blume, Prof. Dr.-Ing. B. Wicht, apl. Prof. Dr.-Ing. G. Payá Vayá
      Team: M.Sc. Moritz Weißbrich, M.Sc. Lars-Christian Kähler
      Year: 2019
      Sponsors: BMBF
      Lifespan: October 2018 - March 2021
    • ZuSE-KI-mobil
      Für Zukunftsaufgaben wie das autonome Fahren oder Industrie 4.0 müssen immer größere Mengen an Daten von einer steigenden Anzahl von Sensoren mit Hilfe komplexer Algorithmen und künstlicher Intelligenz (KI) in kürzester Zeit analysiert werden. Die entsprechenden Prozessoren müssen aber nicht nur bei der Rechenleistung, sondern auch hinsichtlich Energieeffizienz, Zuverlässigkeit, Robustheit und Sicherheit hohe Anforderungen erfüllen, die über aktuelle Möglichkeiten weit hinausgehen. Die ZuSE-Projekte des BMBF sollen den dringenden Bedarf der Anwenderbranchen an zukunftsfähigen, vertrauenswürdigen Prozessoren decken, die auf ihre spezifischen Aufgaben zugeschnitten und hoch performant sind. Ziel des Vorhabens ist die Entwicklung einer Prozessorplattform für die Entwicklung hoch performanter Elektronik für rechenintensive KI-Anwendungen. Als Kernkomponente wird ein KI-Beschleuniger mit einer flexiblen, erweiterbaren und skalierbaren System-on-Chip –Architektur (SoC) entwickelt. Um einen niedrigen Energieverbrauch zu erreichen, wird der Beschleuniger für KI-Algorithmen im Bereich des autonomen Fahrens optimiert und in der energieeffizienten 22-nm-FDX-Halbleitertechnologie gefertigt. Darüber hinaus wird ein Ökosystem aufgebaut, das ein Entwicklungssystem sowie ein deutsches Partnernetzwerk mit Know-how im KI-Hardware-Entwurf vereint. Die Flexibilität und Skalierbarkeit der Leistungsdaten der Prozessorplattform wird anhand von Demonstratoren verifiziert. Der rechenstarke KI-Beschleuniger, die flexible und skalierbare SoC-Architektur sowie das Ökosystem bilden eine Plattform für die kostengünstige Entwicklung anwendungsspezifischer KI-Hardware in Deutschland und sind für zukünftige Innovationen breit einsetzbar.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: Matthias Lüders, M.Sc., Nicolai Behmann, M.Sc.
      Year: 2020
      Sponsors: BMBF
      Lifespan: Mai 2020 - April 2023
    • ZuSE-KI-AVF - Anwendungsspezifischer KI-Prozessor für die intelligente Sensorsignalverarbeitung im autonomen Fahren
      Innovative Fahrerassistenzsysteme erfordern neue, leistungsfähige Hardwareplattformen, die in der Lage sind, hochauflösende und mehrdimensionale Datenmengen in Echtzeit zu verarbeiten. Vielfältige Sensorik wie Kamera, Lidar oder Radar führt zu deutlich voneinander abweichenden Anforderungen, denen mit anwendungsspezifischer Hardware begegnet werden kann. Mit dem Ziel der Entwicklung einer solchen Hardware auf Basis einer skalierbaren und flexibel programmierbaren Architekturplattform hat das IMS erfolgreich an der ZuSE-Ausschreibung des BMBF zu Themen der künstlichen Intelligenz teilgenommen. In der Rolle der Projektleitung arbeitet das Institut in einem Konsortium an einer Open-Source Vektorprozessorarchitektur, die sich besonders für ressourcenintensive KI-Algorithmen eignet. Durch die vertikale Verarbeitung von Datenvektoren und komplexe Adressierungsmodi können neuronale Netze effizient berechnet werden. Für den Einsatz als Embedded-IP-Core in kommerziellen SoCs werden zudem Aspekte der funktionalen Sicherheit und IP-Security betrachtet. Auch die Entwicklung eines Compilers und eines effizienten Speichercontroller sind Teil des Projektes ZuSE-KI-AVF. Das IMS entwickelt an der Systemarchitektur, der Konzeption und Implementation von Algorithmen wie der Verarbeitung von Lidar-Punktwolken sowie einer Demonstration der Architektur auf Basis einer FPGA-Beschreibung.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: M.Sc. Sven Gesper, M.Sc. Oliver Renke, M.Sc. Christoph Riggers, M.Sc. Gia Bao Thieu
      Year: 2020
      Sponsors: BMBF
      Lifespan: Oktober 2020 - September 2023

    Analog/Mixed-Signal-Design

    • GEBO - High Temperature Electronic
      In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Ing. Rochus Nowosielski
      Year: 2014
      Lifespan: 2009-20111
    • Multi-Energy Harvesting (MEH) - A Flexible Platform for Energy Harvesting in Home Automation
      In this project, a platform concept for intelligent home automation components is developed, which can serve as a basis for next-generation sensors and actors. The main characteristic of this platform concept is ultra-low power consumption and ultra-low voltage operation. In combination with harvested energy from multiple sources (multi-energy harvesting), an extended lifetime and reduced battery cell requirements become possible compared to current systems.
      Leaders: Prof. Dr.-Ing. H. Blume, Prof. Dr.-Ing. B. Wicht, apl. Prof. Dr.-Ing. G. Payá Vayá
      Team: M.Sc. Moritz Weißbrich, M.Sc. Lars-Christian Kähler
      Year: 2019
      Sponsors: BMBF
      Lifespan: October 2018 - March 2021

    Design Space Exploration

    • EFdiS – Use of airborne SAR with digital interface
      The goal of this research project is the processing of FMCW sensor signals. The first step is intended to digitize the analog data on board through a suitable expansion card. In the second step, the digitized data is to be processed on board, and thus converted to an aerial image.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Ing. M. Wielage
      Year: 2014
      Lifespan: October 2012 - December 2014
    • OPARO
      In the development of integrated, programmable circuits, the optimization of power dissipation and temperature distribution is becoming increasingly important. So far, however, these can only be determined by very time-consuming simulations. Therefore, precise models for the determination of power dissipation shall be developed and mapped together with the functional emulation on FPGAs. By accelerating the determination of power dissipation and temperature distribution, specific optimizations of the architecture and the application code can then be made taking real input data into account.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Wirtsch.-Ing. Sebastian Hesselbarth
      Year: 2014
    • Digital Video-processing for automation in agriculture
      Within this project, algorithms are developed, architectures explored and a final hardware-platform designed and evaluated. The overall system will be tested in a field test.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: J. Hartig, S. Gesper
      Year: 2019
      Lifespan: a 2017-2019
    • Compact Realtime SAR-Image processor
      The goals of this project are the generation and compression of high resolution Synthetic Aperture Radar (SAR) images under real time conditions. Compared to camera based electro-optical sensors, a SAR system operates almost independent from daylight and weather conditions. State-of-the-art SAR sensor systems achieve spatial resolutions up to 10 cm at 10 km altitude. By using FPGAs for high performance digital signal processing tasks, aerial images can be generated in real time even in case of very large image dimensions.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: F. Cholewa, C. Fahnemann, N. Rother
      Year: 2020
      Lifespan: 2008-2020

    Driver Assistance Systems

    • OpenFAS
      In the scope of this project, a library of modules for driver assistence systems, based on a multicore processor architecture will be created. The project is in collaboration with the videantis corporation.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: Dipl.-Ing. Christopher Bartels
      Year: 2012
      Sponsors: "Zentrales Innovationsprogramm Mittelstand" des Bundesministeriums für Wirtschaft und Technologie (BMWi)
      Lifespan: Juni 2012 - Oktober 2013
    • DESERVE - Development Platform for Safe and Efficient Drive
      DESERVE is a project funded by the European Union. The aim of the project is the promotion and evolution of advanced driver assistance systems (ADAS). These systems are devoted to support the driver in the safe control of the vehicle. For this purpose, the DESERVE platform is planned to be developed. This platform will be the base for future development of advanced driver assistance systems in Europe.
      Leaders: Prof. Dr.-Ing. H. Blume, apl. Prof. Dr.-Ing. G. Payá Vayá
      Team: Florian Giesemann, Frank Meinl, Nico Mentzer
      Year: 2013
      Sponsors: Europäische Union, Bundesministerium für Bildung und Forschung
      Lifespan: September 2012 - August 2015
    • ASEV
      The goal of this sub-project of the BMBF project "Automatic Situation Interpretation for Event Triggered Video Surveillance" is to elaborate a concept for a hardware architecture that enables a SIFT (Scale Invariant Feature Transform) feature extraction under application-specific processing conditions as performance and power consumption. SIFT features offer a good basis for robust object identification and tracking for event triggered video surveillance. The field of application is thereby the airport apron, which is highly relevant to security. The concept was implemented on a FPGA-based hardware platform to build a demonstrator which was tested at the end of the project at the airport of Braunschweig.
      Leaders: Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: Dipl.-Ing. Nico Mentzer
      Year: 2014
      Sponsors: Bundesministerium für Bildung und Forschung (BMBF)
      Lifespan: Mai 2010 - April 2013
    • Efficient Hardware Architectures for Fast Image Sequence Analysis
      In practice, general reliability of modern driver assistance systems under arbitrary traffic, weather and illumination conditions often is a problem. Because more robust algorithms are computationally very intensive, this project deals with the examination of heterogenous hardware architectures and the evaluation of new mechanisms for complex applications in the field of camera-based driver assistance.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Julian Hartig
      Year: 2014
      Sponsors: Hans L. Merkle Stiftung
      Lifespan: February 2014 - February 2017
    • mDAS - Implementation of a real-time demonstrator for multicore-based driver assistance systems
      The goal of this Project is the conceptual design of a real-time mutlicore-based demonstrator for video-based driver assistance algorithms. Therefore, different performance metrics will be displayed in order to compare platform-specific performance characteristics.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: Dipl.-Ing. Jakob Arndt
      Year: 2014
      Sponsors: Siemens AG
      Lifespan: February 2014 - August 2014
    • ZIM Dream Chip Technologies GmbH
      In cooperation with Dream Chip Technologies GmbH, Garben, Germany, the Institute of Microelectronic Systems develops with funding from the Federal Ministry of Economic Affairs and Energy a camera system with integrated algorithms for high quality real time motion estimation in the area of driver assistance systems.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Gregor Schewior, Nicolai Behmann
      Year: 2015
      Sponsors: Bundesministerium für Wirtschaft und Energie
      Lifespan: September 2015 - December 2016
    • THINGS2DO - THIN but Great Silicon 2 Design Objects
      THINGS2DO is an ENIAC project, funded by the European Union and the Federal Ministry of Education and Research. The project aims to develop the new Fully Depleted Silicon On Insulator (FD-SOI) technology and the corresponding tool environment for high efficient and highly integrated circuits. The capabilities of the technology are further demonstrated through a demonstrator in the area of Advanced Driver Assistance Systems (ADAS).
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Gregor Schewior, Nicolai Behmann
      Year: 2016
      Sponsors: Europäische Union, Bundesministerium für Bildung und Forschung
      Lifespan: February 2016 - March 2018
    • Adaptive blendfreie HD-Scheinwerfer
      In diesem Projekt werden Signalverarbeitungsalgorithmen für hochauflösende Scheinwerfer entworfen und echtzeitfähig auf verschiedenen Hardwareplattformen implementiert. Durch die adaptiven Scheinwerfersysteme wird unter Anderem eine Blendung von Verkehrsteilnehmern verhindert und die Sicherheit im Straßenverkehr erhöht.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: Jens Schleusner, M.Sc.
      Year: 2017
      Lifespan: 2017-2021
    • Verlässliche Mobilität: Mobiler Mensch im Spannungsfeld zwischen Autonomie, Vernetzung und Security
      Die Mobilität der Zukunft basiert wesentlich auf dem hochautomatisierten Fahren und damit auf verlässlichen „Advanced Driver Assistance Systems“ (ADAS). Diese Fahrerassistenzsysteme benötigen eine zuverlässige Erfassung der Umwelt durch die Sensoren der Fahrzeuge, um die erforderliche Verlässlichkeit zu erreichen. Neben Radar- und Lidar-Sensoren verfügen moderne Fahrzeuge über eine Vielzahl von Kameras, die geometrische und semantische Informationen zur Umgebung bereitstellen. Diese verschiedenen Datenströme werden im Anschluss von Datenfusionsalgorithmen auf Fahrzeuginterner Hardware weiterverarbeitet. Zur Berechnung verlässlicher Ergebnisse muss das Gesamtsystem der Signalverarbeitung aus Hardware und Software verlässlich sein. Das Fachgebiet Architekturen und Systeme des IMS wird im Rahmen des Projektes „Mobiler Mensch“ zu diesen Teilaspekten eines Systems zur verlässlichen Datenverarbeitung forschen.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: Jens Schleusner, M.Sc.
      Year: 2017
      Lifespan: 2017-2019
    • PARIS - PARallele Implementierungs-Strategien für das Hochautomatisierte Fahren
      In diesem Projekt steht das Systemdesign von Fahrerassistenzsystemen vom Szenrio bis hin zur Architektur im Fokus. Es werden sowohl neuartige selbstlernende und Sensorfusions-Algorithmen, als auch eine innovtive Prozessorarchitektur entwickelt. Darüber hinaus werden Entwicklungsschritte für eingebettete MPSoC-Applikationen, wie Architektur-Mapping und Simulationsmethoden, entwickelt.
      Leaders: Prof. Dr.-Ing. Holger Blume, Dipl.-Ing. Jakob Arndt
      Team: Dipl.-Ing. Jakob Arndt
      Year: 2017
      Sponsors: BMBF
      Lifespan: 04.2017 - 03.2020

    Biomedical Engineering

    • Real-time, low-latency sonification of complex movements
      The goal of this research project in the field of biomedical engineering is to generate an auditory feedback (sonification) of human movements. The IMS focuses on examing the performance of different hardware platforms for this application. Relevant performance parameters are the platforms power dissipation and the overall latency. Finally, the project goal is to enhance stroke rehabilitation by additionally providing auditory arm movement feedback. This could lead to shortened rehabilitation periods. Furthermore, the mobile hardware platform developed at the IMS allows home based rehabilitation.
      Leaders: Prof. Dr.-Ing. Blume
      Team: Dipl.-Ing. (FH) H.-P. Brückner
      Year: 2013
      Sponsors: Europäischer Fonds für regionale Entwicklung (EFRE)
      Lifespan: February 2011 - June 2013
    • BIOFABRICATION for NIFE
      BIOFABRICATION for NIFE ist ein interdisciplinary research network between the Hanover Medical School, the Leibniz University of Hanover and the Hanover University of Music, Drama and Media. The goal of this research network is to achieve methods for growing biocompatible organic implants with heavily reduced rejection reactions.
      Leaders: Prof. Dr.-Ing. Blume
      Team: Dipl.-Ing. Christian Leibold
      Year: 2014
      Sponsors: VolkswagenStiftung and County Lower Saxony
      Lifespan: May 2013 - June 2018
    • Hearing4All
      The joint venture "Hearing4all" that the IMS-AS participates in with multiple sub-projects, has been chosen as one of the federal cluster of excellence projects Friday June 15th 2012. In the scope of this project the IMS-AS aims to develop high-performance and low-power processor architectures for digital hearing systems, such as cochlear implants or hearing aids.
      Leaders: Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: M.Sc. C. Seifert, Dipl.-Ing. L. Gerlach
      Year: 2015
      Lifespan: November 2012 - December 2018
    • Optogenetic
      Within this cooperation with the Institute of Technical Chemistry and the Institute of Quantum Optics of the Leibniz Universität Hannover, methods are being studied to control the behavior of intracellular processes from the outside with light. Optogenetics can be used to specifically modify light-insensitive cells in order to respond to the influence of light. Due to the common previous experience between the project partners, especially optogenetic questions in the context of tissue engineering are focussed.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: Marc-Nils Wahalla, Dipl.-Ing.
      Year: 2016
    • Efficient Real-time Processing of EEG-Signals
      A brain-computer interface (BCI) is a system that generates signals to control an artificial system based on measurements of the activity of the central nervous system, for example, to replace, enhance or supplement certain tasks of human action. Modern BCIs are often based on the decoding or interpretation of EEG signals, as such systems are both non-invasive and cost-effectively available. These sensors detect a variety of independent, superimposed signals that make their immediate use for controlling a digital system difficult. Therefore, each application and corresponding application environment requires specifically designed and customized algorithms. This project therefore investigates methods for the efficient real-time processing of EEG signals. For this purpose, the Institute of Microelectronic Systems is developing a complete system of dedicated, configurable hardware in combination with a signal-processing framework specially adapted for the processing of EEG signals.
      Leaders: Prof. Dr.-Ing. Holger Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: Marc-Nils Wahalla, Dipl.-Ing.
      Year: 2017
    • ZIM D-Sense - Development of a Testing System for the Diagnosis of Sensorimotor Regulation Abilities in Athletes
      The aim of the project is to develop a mobile diagnostics system which can be used to to assess the sensorimotor regulation abilities in athletes. The system should consist of multiple sensor units and allow the athlete or coach to quickly and precisely perform different functional sensorimotor tests. The sensor units can be placed at different points on or next to the subject's body, depending on the concrete test being performed. Also depending on the test, different algorithms are to be used for classifying and evaluating the measurements from the sensor units. A database helps the user to interpret the test results and provides reference values for risk assessments regarding injuries.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: M.Sc. Fritz Webering
      Year: 2017
      Sponsors: „Zentrales Innovationsprogramm Mittelstand“ of the BMWi - Federal Ministry for Economic Affairs and Energy
      Lifespan: 2017-2019
    • Smart Hearing Aid Processor (Smart HeaP)
      In the Smart Hearing Aid Processor (Smart HeaP) project, a novel hearing aid processor is designed, developed and built which, despite its simple programmability and wireless Bluetooth interface, is characterized by low power consumption and high computing power.
      Leaders: Prof. Dr.-Ing. H. Blume, apl. Prof. Dr.-Ing. G. Payá Vayá
      Team: Dipl.-Ing. L. Gerlach, M.Sc. J. Karrenbauer
      Year: 2018
      Sponsors: BMBF
      Lifespan: April 2018 - April 2021
    • D-Sense-DL
      Im bereits abgeschlossenen biomedizintechnischen Kooperationsprojekt "D-Sense" wurde ein mobiles Diagnose-System zur Beurteilung der sensomotorischen Regulationsfähigkeit von Sportlern entwickelt. Dieses System aus mehreren Inertialsensoren und speziell entwickelten Algorithmen erlaubt es, verschiedene sensomotorische Testverfahren ohne Anleitung durch einen geschulten Tester selbst durchzuführen. Ziel des aktuell genehmigten Folgeprojekts D-Sense-DL ist es, im Vorfeld der Markteinführung die Validität dieses Systems im Vergleich zu klassischen Messmethoden derselben Testverfahren zu untersuchen. Hierzu wird eine erweiterte Probandenstudie mit einem im Vergleich zum letzten Projekt noch weiter verbesserten Testsystem durchgeführt.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: M.Sc. Fritz Webering
      Year: 2020

    System Design

    • GEBO - High Temperature Electronic
      In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: Dipl.-Ing. Rochus Nowosielski
      Year: 2014
      Lifespan: 2009-20111
    • Efficient Real-time Processing of EEG-Signals
      A brain-computer interface (BCI) is a system that generates signals to control an artificial system based on measurements of the activity of the central nervous system, for example, to replace, enhance or supplement certain tasks of human action. Modern BCIs are often based on the decoding or interpretation of EEG signals, as such systems are both non-invasive and cost-effectively available. These sensors detect a variety of independent, superimposed signals that make their immediate use for controlling a digital system difficult. Therefore, each application and corresponding application environment requires specifically designed and customized algorithms. This project therefore investigates methods for the efficient real-time processing of EEG signals. For this purpose, the Institute of Microelectronic Systems is developing a complete system of dedicated, configurable hardware in combination with a signal-processing framework specially adapted for the processing of EEG signals.
      Leaders: Prof. Dr.-Ing. Holger Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: Marc-Nils Wahalla, Dipl.-Ing.
      Year: 2017
    • ZIM D-Sense - Development of a Testing System for the Diagnosis of Sensorimotor Regulation Abilities in Athletes
      The aim of the project is to develop a mobile diagnostics system which can be used to to assess the sensorimotor regulation abilities in athletes. The system should consist of multiple sensor units and allow the athlete or coach to quickly and precisely perform different functional sensorimotor tests. The sensor units can be placed at different points on or next to the subject's body, depending on the concrete test being performed. Also depending on the test, different algorithms are to be used for classifying and evaluating the measurements from the sensor units. A database helps the user to interpret the test results and provides reference values for risk assessments regarding injuries.
      Leaders: Prof. Dr.-Ing. H. Blume
      Team: M.Sc. Fritz Webering
      Year: 2017
      Sponsors: „Zentrales Innovationsprogramm Mittelstand“ of the BMWi - Federal Ministry for Economic Affairs and Energy
      Lifespan: 2017-2019
    • ZuSE-KI-mobil
      Für Zukunftsaufgaben wie das autonome Fahren oder Industrie 4.0 müssen immer größere Mengen an Daten von einer steigenden Anzahl von Sensoren mit Hilfe komplexer Algorithmen und künstlicher Intelligenz (KI) in kürzester Zeit analysiert werden. Die entsprechenden Prozessoren müssen aber nicht nur bei der Rechenleistung, sondern auch hinsichtlich Energieeffizienz, Zuverlässigkeit, Robustheit und Sicherheit hohe Anforderungen erfüllen, die über aktuelle Möglichkeiten weit hinausgehen. Die ZuSE-Projekte des BMBF sollen den dringenden Bedarf der Anwenderbranchen an zukunftsfähigen, vertrauenswürdigen Prozessoren decken, die auf ihre spezifischen Aufgaben zugeschnitten und hoch performant sind. Ziel des Vorhabens ist die Entwicklung einer Prozessorplattform für die Entwicklung hoch performanter Elektronik für rechenintensive KI-Anwendungen. Als Kernkomponente wird ein KI-Beschleuniger mit einer flexiblen, erweiterbaren und skalierbaren System-on-Chip –Architektur (SoC) entwickelt. Um einen niedrigen Energieverbrauch zu erreichen, wird der Beschleuniger für KI-Algorithmen im Bereich des autonomen Fahrens optimiert und in der energieeffizienten 22-nm-FDX-Halbleitertechnologie gefertigt. Darüber hinaus wird ein Ökosystem aufgebaut, das ein Entwicklungssystem sowie ein deutsches Partnernetzwerk mit Know-how im KI-Hardware-Entwurf vereint. Die Flexibilität und Skalierbarkeit der Leistungsdaten der Prozessorplattform wird anhand von Demonstratoren verifiziert. Der rechenstarke KI-Beschleuniger, die flexible und skalierbare SoC-Architektur sowie das Ökosystem bilden eine Plattform für die kostengünstige Entwicklung anwendungsspezifischer KI-Hardware in Deutschland und sind für zukünftige Innovationen breit einsetzbar.
      Leaders: Prof. Dr.-Ing. Holger Blume
      Team: Matthias Lüders, M.Sc., Nicolai Behmann, M.Sc.
      Year: 2020
      Sponsors: BMBF
      Lifespan: Mai 2020 - April 2023

    Reconfigurable Architectures

    • Circuit Design and Physical Design for a Novel FPGA Architecture
      Evaluation and analysis of the implemtability and performance of a new type of field programmable gate array (FPGA).
      Leaders: Prof. Dr.-Ing. H. Blume, apl. Prof. Dr.-Ing. G. Payá Vayá
      Team: B. Bredthauer, C. Spindeldreier
      Year: 2013
      Sponsors: Federal Ministry of Education and Reserach
      Lifespan: May 2013 - June 2014
    • TUKUTURI
      In the TUKUTURI-project, a for ASIC-synthesis optimized VHDL-description of a soft core processor architecture will be optimized for FPGA synthesis. The suitability of special functional units for specific applications with regard to performance and area consumption will be analyzed.
      Leaders: Jun.-Prof. Dr.-Ing. G. Payá-Vayá
      Team: M. Sc. Florian Giesemann
      Year: 2014
      Sponsors: Wege in die Forschung II