Institute of Microelectronic Systems Research
Efficient Hardware Architectures for Fast Image Sequence Analysis

Efficient Hardware Architectures for Fast Image Sequence Analysis

Led by:  Prof. Dr.-Ing. H. Blume
Team:  Julian Hartig
Year:  2014
Date:  17-03-14
Funding:  Hans L. Merkle Stiftung
Duration:  February 2014 - February 2017
Is Finished:  yes

In practice, general reliability and robustness of modern driver assistance systems under arbitrary traffic, weather and illumination conditions often is a problem. In the future, there is a need for more complex algorithms to provide more reliable information as a basis to make autonomous decisions in the car. Cost-efficient stereo camera systems with high resolution are capable of providing sufficient image data, which can be used for various applications. However, often there is a lack of computation power in the subsequent image processing hardware to evaluate the data with robust methods at high framerate (quick reactivity of the system) and at low power consumption (<10W).

This project deals with the examination of heterogenous hardware architectures and the evaluation of new mechanisms for complex, computationally intensive applications in the field of camera-based driver assistance. One application is the joint processing of optical flow and disparity estimation on the basis of stereo image sequences for motion capture of objects in 3D space (scene flow analysis).