Institute of Microelectronic Systems Research
Integrated Circuit Design for a High-voltage Class-D amplifier (SmartAmp)

Integrated Circuit Design for a High-voltage Class-D amplifier (SmartAmp)

Led by:  Prof. Dr.-Ing. Bernhard Wicht
Team:  Dietmar Spiger
Year:  2022
Funding:  Industrie
Duration:  01.06.2021-31.05.2023