Institute of Microelectronic Systems Research
Integrated Circuit Design for a High-voltage Class-D amplifier (SmartAmp 2)

Integrated Circuit Design for a High-voltage Class-D amplifier (SmartAmp 2)

Led by:  Prof. Dr.-Ing. Bernhard Wicht
Team:  Dietmar Spiger
Year:  2025
Date:  21-05-25
Funding:  Industrie
Duration:  01.06.2024 - 30.06.2026