Stochastic Processor

Quantification of the Trade-off between Energy and Exactness in Computer Vision Processor Architectures Enhanced with Stochastic Computing Mechanisms

Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits. Typical implementation constraints are related to operation frequency or operation voltage. Reducing the operation voltage will significantly reduce the power consumption and increase the error rate (i.e., malfunctioning). How to design "imprecise" hardware systems, in order to reduce the error rate while exposing hardware variability, is the main challenge of stochastic computing. Understanding all these hardware design trade-offs and their implication on the target application resulting from the imprecise computation is mandatory.

The use of stochastic computing in processor architectures and computer vision applications requires the study of new hardware design techniques at all design levels (i.e., application, processor architecture, and chip layout). This project proposes to quantify the energy-exactness trade-offs in computer vision processor architectures enhanced with stochastic computing mechanisms. For this purpose, two different processor architectures (i.e., a VLIW architecture enhanced with SIMD instructions and a Vector Processor architecture), which orthogonally exploit the data parallelism inherent in computer vision algorithms will be studied. Different processing characteristics result in different hardware mechanisms that require different stochastic computing approaches in order to increase their performance and/or energy efficiency. Analytical error and power models of the resulting stochastic computing mechanisms will be derived to estimate the computation exactness and power consumption of both processor architectures, respectively. Moreover, FPGA-based rapid prototyping will be used to accelerate the verification and analysis of the processing performance of both processor architectures. Furthermore, the computation errors introduced by the stochastic mechanisms and the power consumption models, taking the internal switching activity into account, will be also emulated. Several feature extraction algorithms with different quality, reliability, and cost-effectiveness for object detection and tracking will be used to evaluate the influence of the stochastic computing errors. Finally, this project will allow not only to find and understand the optimal stochastic processor architecture for the exemplary feature extraction algorithm, but also to identify new stochastic computing mechanisms for different processor architecture types especially suited for computer vision applications.