A Hardware/Operating System Co-Design Approach for Energy Optimization in Harsh Environments

The increasing demand for in-situ data processing in harsh and remote environments - such as deep-well drilling operations - is raising the need for autonomous electronic systems capable of reliable control and data processing. Since electrical power from sources, such as generators, is not available in all scenarios, these systems rely on local power sources, such as batteries. Energy efficiency is therefore a primary design constraint. To ensure robustness across a wide temperature range (-40°C to 175° C) and under mechanical stress, we employ 180 nm SOI technology, which is considered state of the art for harsh-environment applications [1]. However, this technology imposes considerable limitations on energy-saving strategies. In particular, leakage currents are negligible (1 % of system power), which renders common techniques such as race-to-completion combined with aggressive power gating largely ineffective. Our evaluation confirms that executing tasks quickly at high clock rates and powering down afterward provides little energy benefit in this context. Instead, we investigate alternative approaches better suited to the characteristics of this SOI technology. Specifically, operating the processor at the lowest feasible supply voltage and frequency significantly reduces dynamic energy per cycle. Moreover, the wide thermal operating range enables temperature-dependent voltage scaling, providing for further energy savings. We propose a HW/OS co-design approach in which a RISC-V processor is extended with hardware support for dynamic voltage and frequency control. These controls are exposed to the OS, enabling fine-grained, workload-aware energy management while ensuring system reliability. The resulting platform adapts its voltage-frequency operating points to ambient temperature, offering a robust and efficient power solution for autonomous computing in harsh environments. Initial simulations show possible energy savings up to 48 %, compared to the race-to-completion approach.