Enhancing Static Task Scheduling for Pipelined Cyclic Executions on Heterogeneous Architectures

Along with the increase in software complexity comes an increasing number of heterogeneous hardware systems, even in real-time safety-critical embedded systems. Programming these heterogeneous systems optimally with respect to resource utilization and overall latency poses a considerable challenge for the developers, and the limited resources in embedded systems only complicate matters. Static scheduling is a promising prospect for maximizing the safety compliance of the final schedule. In earlier work, we have shown that the static scheduling methods found in the literature are capable of calculating near-optimal schedules quickly using a theoretical graph representation of the software. These methods do, however, only schedule a single execution for minimum latency. In environments where the same software is executed continuously, pipelining subsequent executions can often lead to higher throughput. In this paper, we present a novel methodology leveraging known scheduling algorithms to calculate pipelined executions with higher throughput. We propose a model extension that interleaves frames of execution in the same graph in order to utilize parallelism and pipelining effects, and use this extended model to increase the throughput by up to 29.77 %. This method relies on a computationally hard-to-find cut through the graph representation. As such, we further present an approach to reduce the complexity of the problem and approximate the optimum with an error of only 6.3% in 4.7% of the runtime.