The goal of this student lab is the design of basic image processing algorithms with VHDL and its emulation on a FPGA prototyping board. Fundamental VHDL skills are taught and the basic methodology for implementing image processing algorithms on a FPGA prototyping board is presented. The processing results are visualized using a graphical user interface (GUI), which is also used for verification of the students projects. A logic analyzer will be used for debugging the design.
The project tasks are carried out in a group of 2 persons at fixed lab times (4 hours each).
The laboratory includes four exercises:
1. Exercise: Seconds counter with decimal output on a 7-segment display
2. Exercise:Finite State Machine (FSM) - traffic lights and coin changer
3. Exercise: Digital image processing - point operators (inverting, binarization, contrast stretching)
4. Exercise: Digitale image processing - locale operators (e.g., gaussian filterung)
Registration for the laboratory FPGA prototyping is done by the Institute of Systems Engineering - Department of realtime systems (see Hardware-Praktikum).
The date of the introductory event is given by the Institute of Systems Engineering - Department of realtime systems (see Hardware-Praktikum). The participation at the introductory event is mandatory.
The lab notes will be distributed at the introductory event. They are also available at Stud.IP (event name: Miniprojekt FPGA-Prototyping).