Microelectronic - Chipdesign
The project-oriented laboratory Microelectronics - Chipdesign addresses students of electrical and computer engineering, as well as students of other engineering disciplines and is offered in the summer term.
Based on the practical application of a weather station, which captures temperature, barometric pressure and time data (DCF 77) and can be controlled through LCD and keypad, all steps of chip development are experienced in a generic way. The project's structure follows realistic development scenarios: Smaller tasks are worked on in independent groups. The groups' results and experiences will be shared among another during the following development steps to achieve the project goal together.
The laboratory is divided in two different phases. Each phase consists of an interactive self study part in small groups (supervised by IMS staff), as well as interactive tutorials.
Phase 1: Module Implementation
After the kick-off in April implementation of the individual modules will begin. There are going to be special introductions in this development phase regarding VHDL design, testbenches and FPGA emulation. The first phase's intermediate target are VHDL-described modules, allowing for operation of the weather station.
Phase 2: Backend and Prototyping
Following the peripheral module implementation, different groups work on the following topics:
- VHDL module integration and FPGA emulation (Altera DE2 Development and Education Board),
- PCB design and peripheral integration,
- Synthesis and Back-End-Flow using a library of standard ASIC cells,
- software for microcontroller and PC.
Finally the complete weather station will be thoroughly tested using Logic Analyzers on a collaborative lab day.
Soft- and hardware tools to be used in this project
- Altera® Quartus II®
- Mentor Graphics® ModelSim®
- Synopsys® Design Vision™
- Cadence® SoC Encounter™
- Cadsoft EAGLE
- Sigasi Studio
- Logic analyzers
Following the registration on the central registration page (Link), students have to provide more information regarding previous knowledge on this homepage in a mandatory pre-test starting March 26th till April 8th. The link will also be send by the central registration system.
The number of participants is limited. The available seats will be awarded due to the online lab registration. Aspects like progress in the study program are considered.