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Logo: Institut für Mikroelektronische Systeme
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Logo: Institut für Mikroelektronische Systeme
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Publikationen von apl. Prof. Dr.-Ing. Guillermo Payá Vayá

Bücher

2017

Payá-Vayá, G. (Ed.); Blume H. (Ed.) (2017): Towards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems weitere Informationen
DOI: 10.13052/rp-9788793519138
ISBN: 9788793519138

Buchbeiträge

Badstübner, F.; Ködel, R.; Maurer, W.; Kunert, M.; Rolfsmeier, A.; Perez, J.; Giesemann, F.; Payá Vayá, G.; Blume, H.; Reade, G. (2017): The DESERVE Platform: A Flexible Development Framework to Seemlessly Support the ADAS Development Levels, Towards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems - The DESERVE Approach weitere Informationen

Giesemann, F.; Payá Vayá, G.; Blume, H.; Limmer, M.; Ritter, Werner R. (2017): Deep Learning for Advanced Driver Assistance Systems, Towards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems - The DESERVE Approach weitere Informationen

Mentzer, N.; von Egloffstein, N.; Krüger, L.; Payá Vayá, G.; Blume, H. (2017): Self-Calibration of Wide Baseline Stereo Camera Systems for Automotive Applications, Towards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems - The DESERVE Approach weitere Informationen

2005

Payá-Vayá, G.; Langerwerf, M.; Pirsch, P. (2005): RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration, SAMOS V Workshop 2005, Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, et al., Springer, Berlin Heidelberg (32-40)
DOI: 10.1007/11512622_5
ISBN: 354026969X

Journalbeiträge

2019

Weißbrich, M.; García-Ortiz, A.; Payá-Vayá, G. (2019): Comparing Vertical and Horizontal SIMD Vector Processor Architectures for Accelerated Image Feature Extraction, Journal of Systems Architecture (in print)

Weißbrich, M.; Gerlach, L.; Blume, H.; Najafi, A.; García-Ortiz, A.; Payá-Vayá, G. (2019): FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework, Integration, the VLSI Journal (in print, available online)
DOI: 10.1016/j.vlsi.2019.01.002

2018

Castro Martinez, A.M.; Gerlach, L.; Payá-Vayá, G.; Hermansky, H.; Ooster, J.; Meyer, B.T.  (2018): DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters, Speech Communication
DOI: 10.1016/j.specom.2018.11.006

Mentzer, N.; Mahr, J.; Payá-Vayá, G.; Blume, H. (2018): Online Stereo Camera Calibration for Automotive Vision based on HW-accelerated A-KAZE-feature Extraction, Journal of Systems Architecture (in press)
DOI: 10.1016/j.sysarc.2018.11.003

Najafi, A.; Weißbrich, M.; Payá Vayá, G.; García-Ortiz, A. (2018): Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol.8, Issue 4, pp. 736-745
DOI: 10.1109/JETCAS.2018.2833284

2017

Nolting, S.; Payá-Vayá, G.; Giesemann, F.; Blume, H.; Niemann, S.; Müller-Schloer, C. (2017): Dynamic Self-Reconfiguration of a MIPS-Based Soft-Core Processor Architecture, Journal of Parallel and Distributed Computing weitere Informationen
DOI: 10.1016/j.jpdc.2017.09.013

Payá-Vayá, G.; Bartels, C.; Blume, H. (2017): Small footprint synthesizable temperature sensor for FPGA devices, Journal of Systems Architecture, Volume 76, p. 28–38 weitere Informationen
DOI: 10.1016/j.sysarc.2017.03.005

Weide-Zaage, K.; Payá-Vayá, G. (2017): COTS – Harsh Condition Effects Considerations from Technology to User Level, Adv. Sci. Technol. Eng. Syst. J. 2(3), 1592-1598 (2017)
ISBN: ISSN: 2415-6698

2015

Mentzer, N.; Payá Vayá, G.; Blume, H. (2015): Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction, Journal of Signal Processing Systems
DOI: 10.1007/s11265-015-0986-4

2010

Payá-Vayá, G.; Martín-Langerwerf, J.; Pirsch, P. (2010): A Multi-Shared Register File Structure for VLIW Processors, Journal of Signal Processing Systems, 58(2), Springer New York (215-231)
DOI: 10.1007/s11265-009-0355-2
ISBN: 1939-8018 (Print) 1939-8115 (Online)

Konferenzbeiträge

2019

Behmann, N.; Payá Vayá, G.; Blume, H. (2019): Design Space Exploration for Convolutional Neural Networks on a 22 nm FD-SOI SoC, Embedded World Conference (ewc), Nürnberg

Behmann, N.; Payá Vayá, G.; Blume, H. (2019): CNN Design Space Exploration on Tensilica Vision P6 DSP, Cadence User Conference (CDNLive EMEA 2019), München, Germany

Gerlach, L.; Payá-Vayá, G.; Blume, H. (2019): KAVUAKA: A Low Power Application Specific Hearing Aid Processor, 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019) (accepted for publication), Cuzco, Perú

Gesper, S.; Weißbrich, M., Nolting, S.; Stuckenberg, T.; Jääskeläinen, P.; Blume, H.; Payá-Vayá, G. (2019): Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019 International Conference on, Springer LNCS, Pythagorion, Greece (accepted)

Karrenbauer, J.;Gerlach, L.;Payá-Vayá, G.;Blume, H. (2019): Automated Design Space Exploration of Digital Audio Processors for Hearing Aids, CDNLive 2019, Munich

2018

Herzke, T.; Kayser, H.; Seifert, C.; Maanen, P.; Obbard, C.; Payá-Vayá, G.; Blume, H.; Hohmann, V. (2018): Open Hardware Multichannel Sound Interface for Hearing Aid Research on BeagleBone Black with openMHA: Cape4all, Proceedings of the Linux Audio Conference 2018
DOI: 10.14279/depositonce-7046

Jaaskelainen, P.; Tervo, A.; Paya Vaya, G.; Viitanen, T.; Behmann, N.; Takala, J.; Blume, H. (2018): Transport-Triggered Soft Cores, IEEE Intl. Parallel and Distributed Processing Symposium

Nolting, S.; Gesper, S.; Schmider, A.; Weißbrich, M.; Stuckenberg, T.;Blume, H.; Paya-Vaya, G. (2018): Processor Architecture Tradeoffs for On-Site Electronics in Harsh Environments, CDNLive 2018, Munich

Weißbrich, M.; Najafi, A.; García-Ortiz, A.; Payá Vayá, G. (2018): ATE-Accuracy Trade-Offs for Approximate Adders and Multipliers in Pipelined Processor Datapaths, 2018 Third Workshop on Approximate Computing (AxC18, www.lirmm.fr/axc18)

2017

Gerlach, L.; Marquardt, D.; Payá Vayá, G.; Liu, S.; Weißbrich, M.; Doclo, S.; Blume, H.  (2017): Analyzing the Trade-Off between Power Consumption and Beamforming Algorithm Performance using a Hearing Aid ASIP, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2017 International Conference on, IEEE, Pythagorion, Greece weitere Informationen
DOI: 10.1109/SAMOS.2017.8344615

Giesemann, F.; Payá-Vayá, G.; Gerlach, L.; Blume, H.; Pflug, F.; von Voigt, G. (2017): Using a Genetic Algorithm Approach to Reduce Register File Pressure during Instruction Scheduling, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation 2017 (SAMOS XVII)

Hartig, J.; Payá Vayá, G.; Heymann, H.; Blume, H. (2017): Tool-Supported Design Space Exploration of a Processor System for SIFT-Feature Detection, IEEE International Conference on Consumer Electronics (ICCE), Berlin, 2017
DOI: 10.1109/ICCE-Berlin.2017.8210619

Hartig, J.; Payá Vayá, G.; Mentzer, N.; Blume, H. (2017): Balanced Application-Specific Processor System for Efficient SIFT-Feature Detection, IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVII), Stamatis Vassiliadis Best Paper Award, 2017
DOI: 10.1109/SAMOS.2017.8344614

Najafi, A.; Weißbrich, M.; Payá Vayá, G.; García-Ortiz, A. (2017): A Fair Comparison of Adders in Stochastic Regime, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Nolting, S.; Giesemann, F.; Hartig, J.; Schmider, A.; Payá-Vayá, G (2017): Application-Specific Soft-Core Vector Processor for Advanced Driver Assistance Systems, 27th International Conference on Field-Programmable Logic and Applications 2017, Ghent, Belgium

Nolting, S.; Liu, L.; Payá-Vayá, G. (2017): Two-LUT-Based Synthesizable Temperature Sensor for Virtex-6 FPGA Devices, 27th International Conference on Field-Programmable Logic and Applications 2017, Ghent, Belgium

Seifert, C.; Thiemann, J.; Gerlach, L.; Volkmar, T.; Payá-Vayá, G.; Blume, H.; van de Par, S.  (2017): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a VLIW-SIMD Processor, International Conference on Multimedia and Expo (ICME) 2017, IEEE
DOI: 10.1109/ICME.2017.8019478

Webering, F.; Payá-Vayá, G.; Aditya, E.; Dürre, J.; Blume, H. (2017): An Integrated Heated Testbench for Characterizing High Temperature ICs [Best Flash Presentation Award], ICT.OPEN2017, Amersfoort, Netherlands

Weißbrich, M.; Payá-Vayá, G.; Gerlach, L.; Blume, H.; Najafi, A.; García-Ortiz, A. (2017): FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

2016

Behmann, N.; Seifert, C.; Payá Vayá, G.; Blume, H.; Jääskeläinen, P.; Multanen, J.; Kultala, H.; Takala, J.; Thiemann, J.; van de Par, S. (2016): Customized High Performance Low Power Processor for Binaural Speaker Localization, International Conference on Electronics, Circuits and Systems (ICECS 2016), IEEE

Dürre, J.; Payá Vayá, G.; Blume, H. (2016): Teaching Digital Logic Circuit Design via Experiment-Based Learning - Print your own Logic Circuit, Proceedings of the 20th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2016), Orlando, USA

Gerlach, L.; Payá Vayá, G.; Blume, H. (2016): Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors, 2016 IEEE International Workshop on Signal Processing Systems (SiPS), Dallas, United States weitere Informationen
DOI: 10.1109/SiPS.2016.52

Gerlach, L.; Payá-Vayá, G.; Blume, H. (2016): A Low Latency Multichannel Audio Interface for Low Power SIMD Digital Signal Processors, ICT.OPEN2016, Amersfoort, Netherlands weitere Informationen
ISBN: 978-90-73461-932

Meyer, B. T.; Mallidi, S. H.; Castro Martínez, A. M.; Payá-Vayá, G.; Kayser, H.; Hermansky, H. (2016): Performance Monitoring for Automatic Speech Recognition in Noisy Multi-Channel Environments, 2016 IEEE Spoken Language Technology Workshop (SLT)
DOI: 10.1109/SLT.2016.7846244

Nolting, S.; Payá Vayá, G.; Giesemann, F.; Blume, H. (2016): Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture, 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
DOI: 10.1109/IPDPSW.2016.158

2015

Bartels, C.; Zhang, C.; Payá-Vayá, G.; Blume, H. (2015): A Synthesizable Temperature Sensor on FPGA using DSP-Slices for Reduced Calibration Overhead and Improved Stability, Architecture of Computing Systems (ARCS 2015), Best Paper Award
ISBN: ISBN 978-3-319-16086-3

Gerlach, L.; Payá Vayá, G.; Blume, H. (2015): An Area Efficient Real- and Complex-Valued Multiply-Accumulate SIMD Unit for Digital Signal Processors, 2015 IEEE Workshop on Signal Processing Systems, Hangzhou, China weitere Informationen
DOI: 10.1109/SiPS.2015.7345019

Nolting, S.; Payá-Vayá, G.; Giesemann, F.; Blume, H. (2015): Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015)

Nowosielski, R.; Gerlach, L.; Bieband, S.; Payá-Vayá, G.; Blume, H. (2015): FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design, Proceedings of Design, Automation & Test in Europe (DATE2015), Grenoble, France
ISBN: 978-3-9815-3704-8

Nowosielski, R.; Hartig, J.; Payá-Vayá, G.; Blume, H.; Garcia-Ortiz, A. (2015): Exploring Different Approximate Adder Architecture Implementations in a 250°C SOI Technology, 1st Workshop On Approximate Computing (WAPCO), HiPEAC 2015 weitere Informationen

Pfefferkorn, Daniel; Schmider, Achim; Payá Vayá, Guillermo ; Neuenhahn, Martin; Blume, Holger  (2015): FNOCEE: A Framework for NoC Evaluation by FPGA-based Emulation, SAMOS 2015
DOI: 10.1109/SAMOS.2015.7363663

Seifert, C.; Payá-Vayá, G.; Blume, H.;Herzke, T.;Hohmann, V. (2015): A Mobile SoC-Based Platform for Evaluating Hearing Aid Algorithms and Architectures, Consumer Electronics - Berlin (ICCE-Berlin), 2015 5th IEEE International Conference on

2014

Arndt, O. J.; Becker, D.; Giesemann, F.; Payá Vayá, G.; Bartels, C.; Blume, H. (2014): Performance Evaluation of the Intel Xeon Phi Manycore Architecture Using Parallel Video-Based Driver Assistance Algorithms, Intl. Conf. Embedded Computer Systems (SAMOS XIV), IEEE (125 - 132)
DOI: 10.1109/SAMOS.2014.6893203

Fenzi, M.; Mentzer, N.; Payá Vayá, G.; Nguyen, T.; Risse, T.; Blume, H.; Ostermann, J.; (2014): Automatic Situation Assessment for Event-driven Video Analysis, Proceedings of 11th IEEE International Conference on Advanced Video and Signal-Based Surveillance (2014)
DOI: 10.1109/AVSS.2014.6918641

Giesemann, F.; Paya Vaya, G.; Blume, H.; Limmer, M.; Ritter, W. (2014): A Comprehensive ASIC/FPGA Prototyping Environment for Exploring Embedded Processing Systems for Advanced Driver Assistance Applications, International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS), 2014

Hartig, J.; Gerlach, L.; Payá-Vayá, G.; Blume, H. (2014): Customizing a VLIW-SIMD Application-Specific Instruction-Set Processor for Hearing Aid Devices, IEEE International Workshop on Signal Processing Systems 2014 (SiPS), Belfast, UK
DOI: 10.1109/SiPS.2014.6986072

Mentzer, N.; Payá Vayá, G.; Blume, H.; von Egloffstein, N.; Ritter, W. (2014): Instruction-Set Extension for an ASIP-based SIFT Feature Extraction, Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
DOI: 10.1109/SAMOS.2014.6893230

2013

Dellavale, D.; Leibold, C.; Payá-Vayá, G.; Blume, H.; Alam, M.; Schwabe, K.; Krauss, J. (2013): Optimization of a Phase–to–Amplitude Coupling Algorithm for Real–Time Processing of Brain Electrical Signals, Conference ICT.OPEN 2013, Proceedigns of ICT.OPEN 2013, (68--73) weitere Informationen
ISBN: 978-90-73461-84-0

Nowosielski, R.; Gerlach, L.; Payá-Vayá, G.; Hesselbarth, S.; Blume, H. (2013): Methodology for Observation and Evaluation of Fault Tolerance Implementations inside High Temperature ASICs, Conference ICT.OPEN 2013, Proceedings of ICT.OPEN 2013, (97--101), Eindhoven, Netherlands weitere Informationen
ISBN: 978-90-73461-84-0

Payá-Vayá, G. (2013): ASIP-Architekturen für digitale Hörgerätesysteme – Ergebnisse aus dem Exzellenzcluster Hearing4all, DESIGN&ELEKTRONIK-Entwicklerforum "Electronics goes medical", Tagunsunterlagen DESIGN&ELEKTRONIK-Entwicklerforum "Electronics goes medical"
DOI: www.electronics-goes-medical.de
ISBN: 978-3-645-50123-1

Payá-Vayá, G.; Seifert, C.; Blume, H. (2013): Design of Application-Specific Instruction-Set Processors for Digital Hearing Aid Systems, 1st Russian German Conference on Biomedical Engineering (RGC 2013), Proceedings of 1st Russian German Conference on Biomedical Engineering (RGC 2013), B. Chichkov, E. Fadeeva, L.A. Kahrs, T. Ortmaier, PZH Verlag (32)
ISBN: 978-3-944586-25-0

Seifert, C.; Payá-Vayá, G.; Blume, H. (2013): A Multi-Channel Audio Extension Board for Binaural Hearing Aid Systems, Conference ICT.OPEN 2013, Proceedings of ICT.OPEN 2013, (33--37) weitere Informationen
ISBN: 978-90-73461-84-0

Werner, N.; Payá-Vayá, G.; Blume, H. (2013): Case Study: Using the Xtensa LX4 Configurable Processor for Hearing Aid Applications, Conference ICT.OPEN 2013, Proceedings of ICT.OPEN 2013, (27-32) weitere Informationen
ISBN: 978-90-73461-84-0

2012

Giesemann, F.; Payá-Vayá, G.; Blume, H. (2012): A Hardware/Software Environment for Specializing Dynamic Reconfigurable Generic VLIW-SIMD ASIP Architecture, ICT.OPEN 2012 Conference

Hartig, J.; Payá-Vayá, G.; Blume, H. (2012): Design and Analysis of a Structured-ASIC Architecture for Implementing Generic VLIW-SIMD Processors, ICT.OPEN 2012 Conference weitere Informationen
ISBN: 978-90-73461-80-2

Nolting, S.; Payá-Vayá, G.; Schmädecke, I.; Blume, H. (2012): Evaluation of a Generic Radix-4 CORDIC Coprocessor Tightly Coupled with a Generic VLIW-SIMD ASIP Architecture, ICT.OPEN 2012 Conference

Payá-Vayá, G.; Burg, R.; Blume, H. (2012): Dynamic Data-Path Self-Reconfiguration of a VLIW-SIMD Soft-Processor Architecture, Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) in conjunction with the 2012 International Conference on Field Programmable Logic and Applications (FPL 2012), (26-29) weitere Informationen

2011

Nolting, S.; Vaya, P.; Blume, H. (2011): Optimizing VLIW-SIMD Processor Architectures for FPGA Implementation, ICT.OPEN 2011 Conference (Veldhoven, Netherlands), USB-Proceedings

2010

Payá-Vayá, G.; Martín-Langerwerf, J.; Banz, C.; Giesemann, F.; Pirsch, P.; Blume, H. (2010): VLIW Architecture Optimization for an Efficient Computation of Stereoscopic Video Applications, The 2010 International Conference on Green Circuits and Systems, IEEE (457-462)
ISBN: 978-1-4244-6877-5

Payá-Vayá, G.; Martín-Langerwerf, J.; Blume, H.; Pirsch, P. (2010): A Forwarding-sensitive Instruction Scheduling Approach to Reduce Register File Constraints in VLIW Architectures, Application-specific Systems, Architectures and Processors, 2010. ASAP 2010. 21th IEEE International Conference on, François Charot, Frank Hannig, Jürgen Teich, and Christophe Wolinski, IEEE (151-158)
ISBN: 978-1-4244-6965-9

2009

Payá-Vayá, G.; Martín-Langerwerf, J.; Giesemann, F.; Blume, H.; Pirsch, P. (2009): Instruction Merging to Increase Parallelism in VLIW Architectures, International Symposium on System-on-Chip 2009, Intl. Symposium on System-on-Chip, J. Nurmi, J. Takala, O. Vainio, IEEE (143-146)
DOI: 10.1109/SOCC.2009.5335660
ISBN: 978-1-4244-4465-6

Payá-Vayá, G.; Martín-Langerwerf, J.; Moch, S.; Pirsch, P. (2009): An Enhanced DMA Controller in SIMD Processors for Video Applications, Architecture of Computing Systems - ARCS 2009, Lecture Notes in Computer Science(Vol. 5455/2009), Berekovic et al., Springer Berlin / Heidelberg (159-170)
DOI: 10.1007/978-3-642-00454-4_17
ISBN: 978-3-642-00453-7

2007

Payá-Vayá, G.; Jambor, T.; Septinus, K.; Hesselbarth, S.; Flatt, H.; Freisfeld, M.; Pirsch, P. (2007): CHIPDESIGN - From Theory to Real World, Proceedings of the Workshop on Computer Architecture Education in conjunction with the 34th International Symposium on Computer Architecture, ACM (58-64) weitere Informationen
ISBN: 978-1-59593-797-1

Payá-Vayá, G.; Langerwerf, M.; Pirsch, P. (2007): Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler, ARCS 2007, LNCS 4415, Springer-Verlag, Berlin Heidelberg (254-267)
DOI: 10.1007/978-3-540-71270-1_19
ISBN: 3540712674

Payá-Vayá, G.; Martín-Langerwerf, J.; Pirsch, P. (2007): RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip, 10th EUROMICRO Conference on Digital System Design (DSD 2007): Architectures, Methods and Tools, IEEE Conference Publishing Services, Los Alamitos (California, USA) (215-221)
DOI: 10.1109/DSD.2007.4341471
ISBN: 9780769529783

Payá-Vayá, G.; Martín-Langerwerf, J.; Taptimthong, P.; Pirsch, P. (2007): Design Space Exploration of Media Processors: A Parameterized Scheduler, Proceedings of the Intl. Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), IEEE (41-49)
DOI: 10.1109/ICSAMOS.2007.4285732
ISBN: 1424410584

2004

Patino, M.; Peiro, M.; Ballester, F.; Payá-Vayá, G. (2004): 2D-DCT on FPGA by Polynomial Transformation in Two-Dimensions, Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS '04), 3, IEEE (365-368)
ISBN: 0-7803-8251-X

2003

Cerda, J.; Gadea, R.; Payá-Vayá, G. (2003): Implementing a Margolus Neighborhood Cellular Automata on a FPGA, 7th International Work-Conference on Artificial and Natural Neural Networks (IWANN'03), LNCS - Artificial Neural Nets Problem Solving Methods(2687), Springer Berlin / Heidelberg (121-128)
DOI: 10.1007/3-540-44869-1_16
ISBN: 978-3-540-40211-4

Patino, M.; Peiro, M.; Ballester, F.; Payá-Vayá, G. (2003): Evaluation of 2D-DCT Architecture for FPGA, XVIII Conference on Design of Circuits and Integrated Systems (DCIS 2003), IEEE (557-561)
ISBN: 84-87087-40-X

Payá-Vayá, G.; Peiro, M.; Ballester, F.; Gadea, R.; Colom, R. (2003): New Distributed Arithmetic Discrete Wavelet Packet Transform Architecture, VLSI Circuits and Systems, SPIE International Symposium on Microtechnologies for the New Millennium, 5117, Jose F. Lopez, Juan A. Montiel-Nelson, and Dimitris Pavlidis, SPIE (370-378)
DOI: 10.1117/12.499056
ISBN: 0-8194-4977-6

Payá-Vayá, G.; Peiro, M.; Ballester, F.; Herrero, V.; Colom, R. (2003): New Lifting Folded Pipelined Discrete Wavelet Transform Architecture, VLSI Circuits and Systems, SPIE International Symposium on Microtechnologies for the New Millennium, 5117, Jose F. Lopez, Juan A. Montiel-Nelson, and Dimitris Pavlidis, SPIE (351-360)
DOI: 10.1117/12.499049
ISBN: 0-8194-4977-6

Payá-Vayá, G.; Peiro, M.; Ballester, F.; Herrero, V.; Mora, F. (2003): Lifting Folded Pipelined Discrete Wavelet Packet Transform Architecture, VLSI Circuits and Systems, SPIE International Symposium on Microtechnologies for the New Millennium, 5117, Jose F. Lopez, Juan A. Montiel-Nelson, and Dimitris Pavlidis, SPIE (312-328)
DOI: 10.1117/12.498992
ISBN: 0-8194-4977-6

Payá-Vayá, G.; Peiró, M.; Ballester, F.; Mora, F. (2003): Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA, 13th International Conference on Field Programmable Logic and Application (FPL 2003), LNCS 2778, Springer Berlin / Heidelberg (533-542)
DOI: 10.1007/978-3-540-45234-8_52
ISBN: 978-3-540-40822-2

Payá-Vayá, G.; Peiro, M.; Ballester, J.; Cerda, J. (2003): A New Inverse Discrete Wavelet Packet Transform Architecture, Proceedings of the Seventh International Symposium on Signal Processing and Its Applications (ISSPA'03), II, IEEE (443-446)
DOI: 10.1109/ISSPA.2003.1224909
ISBN: 0-7803-7946-2

2002

Payá-Vayá, G.; Martinez-Peiro, M.; Ballester, J.; Gadea, R.; Herrero, V. (2002): Fast Ethernet Media Access Controller Core, Designers' Forum Proceedings of Design, Automation and Test in Europe (DATE'02), (183-186)

Payá-Vayá, G.; Mocholi, A.; Sanchez, C.; Ibanez, F. (2002): Sensorial Module of a Module Robot based on Ultrasonic Sensors, International Conference on Communication, Electronics and Control (TELEC'02), (95)
ISBN: 84-8138-506-2

Dissertationen

2011

Payá Vayá, G. (2011): Design and Analysis of a Generic VLIW Processor for Multimedia Applications, Informationstechnik, Informationstechnik, Shaker Verlag (194)
DOI: 10.2370/9783844000641
ISBN: 978-3-8440-0064-1

Sonstiges

2019

Gerlach, L.; Karrenbauer, J.; Payá-Vayá, G.; Blume, H.  (2019): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid System, Wirtschaftsempfang der UVN und der Leibniz Universität Hannover weitere Informationen

Gerlach, L.; Payá-Vayá, G.; Blume, H. (2019): The KAVUAKA Hearing Aid Processor, Europractice Activity Report 2018-2019 (http://europractice-ic.com) weitere Informationen

2018

Gerlach, L.; Payá-Vayá, G.; Blume, H. (2018): Analyzing the Trade-Off between Power Consumption and Beamforming Algorithm Performance using a Hearing Aid ASIP, Tensilica Day—Trends in Modern Design of Configurable Processors 2018, Hannover, Germany

Gerlach, L.; Payá-Vayá, G.; Blume, H.  (2018): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid System, Tag der Fakultät - Die akademische Jahresfeier weitere Informationen

Gerlach, L.; Seifert, C.; Payá-Vayá, G.; Blume, H. (2018): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid System, Leibniz-Symposium “Maschinelles Lernen – Intelligente Digitalisierung” weitere Informationen

Gerlach, L.; Seifert, C.; Payá-Vayá, G.; Blume, H. (2018): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid System, Wirtschaftsempfang der UVN und der Leibniz Universität Hannover weitere Informationen

Payá-Vayá, G.; Gerlach, L.; Blume, H. (2018): The KAVUAKA Hearing Aid Processor, Tensilica Day—Trends in Modern Design of Configurable Processors 2018, Hannover, Germany

2017

Gerlach, L.; Payá-Vayá, G.; Blume, H. (2017): Low-Power Optimization of a VLIW-SIMD ASIP for Hearing Aid Devices, Tensilica Day—Trends in Modern Design of Configurable Processors 2017, Hannover, Germany

Payá-Vayá, G.; Roskamp, S.; Webering, F.; Blume, H. (2017): Improving the Processing Performance of a DSP for High Temperature Electronics using Circuit-Level Timing Speculation, Tensilica Day—Trends in Modern Design of Configurable Processors

2016

Gerlach, L.; Nolting, S.; Blume, H.; Payá Vayá, G.; Stolberg, H.; Reuter, C. (2016): A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor Architectures, Technology Transfer in Computing Systems (TETRACOM Technology Transfer Project (TTP), 2016), Prague, Czech Republic

Gerlach, L.; Seifert, C.; Payá-Vayá, G.; Blume, H. (2016): Instruction-Set Extension based on a 2D Sound Source Localization Algorithm on a Low Power Hearing Aid System, Tensilica Day—Trends in Modern Design of Configurable Processors 2016, Hannover, Germany

Mentzer, N.; Payá-Vayá, G.; Blume, H. (2016): Analyzing the Performance-Hardware Trade-off of ASIP-based Image Feature Extraction, Tensilica Day 2016

2015

Gerlach, L.; Payá Vayá, G.; Blume, H. (2015): FPGA-Based Rapid Prototyping for Exploring and Optimizing Hearing Aid Processors, 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), Bremen, Germany

Payá Vayá, G.; Gerlach, L.; Nowosielski, R.; Blume, H. (2015): FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design, 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), Bremen, Germany

2013

Payá-Vayá, G.; Seifert, C.; Blume, H. (2013): Application-Specific Instruction-Set Processors for Ultra-Low-Power Hearing Aid Devices, 26th International System-on-Chip Conference (SOCC 2013) (invited poster and demo presentation)

2012

Mentzer, N.; Payá-Vayá, G.; Blume, H. (2012): An ASIP Approach to Find Local Features in Video-Based Surveillance Applications, Communications Signal Processing Workshop 2012 (CSPW 2012)