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Logo: Institute of Microelectronic Systems
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Logo: Institute of Microelectronic Systems
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Processor Architectures

Smart Hearing Aid Processor (Smart HeaP)

Bild zum Projekt Smart Hearing Aid Processor (Smart HeaP)

Supervisor:

Prof. Dr.-Ing. H. Blume

Researcher:

Dipl.-Ing. L. Gerlach

Duration:

April 2018 - April 2021

Funded by:

BMBF

Brief description:

[Translate to Englisch:] Im Projekt Smart Hearing Aid Processor (Smart HeaP) wird ein neuartiger Hörgeräteprozessor konzipiert, entwickelt und gebaut, der sich trotz seiner einfachen Programmierbarkeit und der drahtlosen Bluetooth-Schnittstelle durch eine geringe Leistungsaufnahme und hohe Rechenleistung auszeichnet.

 

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CHORUS

Bild zum Projekt CHORUS

Supervisor:

Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Duration:

01.11.2018 - 31.03.2021

Funded by:

BMWi

Brief description:

A highly optimized hardware/hoftware module library for intelligent sensor systems in highly automated driver assistance application based on the reconfigurable Dream Chip Technologies DCT10A SoM platform

 

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Hearing4All

Bild zum Projekt Hearing4All

Supervisor:

Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Researcher:

M.Sc. C. Seifert, Dipl.-Ing. L. Gerlach

Duration:

November 2012 - December 2018

Brief description:

The joint venture "Hearing4all" that the IMS-AS participates in with multiple sub-projects, has been chosen as one of the federal cluster of excellence projects Friday June 15th 2012. In the scope of this project the IMS-AS aims to develop high-performance and low-power processor architectures for digital hearing systems, such as cochlear implants or hearing aids.

 

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Stochastic Processor

Bild zum Projekt Stochastic Processor

Supervisor:

Jun.-Prof. Dr.-Ing. G. Payá-Vayá, Prof. Dr.-Ing. Holger Blume

Researcher:

M.Sc. Moritz Weißbrich

Duration:

February 2016 - January 2019

Funded by:

Deutsche Forschungsgemeinschaft (DFG)

Brief description:

Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits.

 

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RAPANUI - Rapid-Prototyping for Media Processor Architecture Exploration

 

Supervisor:

Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Researcher:

M. Sc. Florian Giesemann

Brief description:

Design, implementation, and evaluation of a prototyping-based Designmethodology for processor architectures for digital signal processing.

 

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