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Logo: Institut für Mikroelektronische Systeme
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Logo: Institut für Mikroelektronische Systeme
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Optimization and Evaluation of Application-Specific Microcontroller Architectures for Low-Power AES Encryption

Student:

Pang Zheng

Betreuer:

Moritz Weißbrich

Art der Arbeit:

Master-/Diplomarbeit

Abteilung:

Fachgebiet für Architekturen und Systeme

Bild Optimization and Evaluation of Application-Specific Microcontroller Architectures for Low-Power AES Encryption

Nowadays, transponder-based authentication devices like electronic door locks are in widespread use. The majority of implementations runs on a single battery only, which therefore needs to be replaced in regular intervals of several months. Since electronic door locks are distributed devices, battery replacement is a significant amount of work in large buildings and should be delayed as long as possible. Also from the viewpoint of environment protection, it is desired to reduce the amount of required batteries by increasing the lifetime of each single battery cell.

A promising approach for battery lifetime extension is energy harvesting, i.e., supporting the energy budget of a device with the collection of solar, RF, thermal or kinetic energy from environmental sources. However, the additional yield from these sources is very limited and energy-efficient operation of the device electronics itself becomes mandatory. This also affects the microcontroller architecture used for authentication and communication encryption with the electronic key.

In this master thesis, the concept of Application-Specific Instruction-Set Processors (ASIPs) shall be evaluated for the purpose of AES encryption, which is one significant algorithmic part of the door lock communication firmware. At the IMS, MIPS- and MSP430-compatible processor architecture descriptions are available in VHDL. These architectures are suited to serve as a baseline core for hardware modifications as well as instruction set customization and functional specialization to obtain a low-power, yet programmable and updateable microcontroller implementation for encryption/decryption purposes.

The task of this work is to specialize and optimize the existing MIPS, VLIW-MIPS and NEO430 processor architectures for the AES encryption algorithm. C compiler support is available. In a first step, an AES reference implementation shall be set up for all architectures and the correct functionality shall be verified with suitable test cases. The second part of this work involves application software and processor hardware optimization and specialization. Profiling and evaluation of the performed actions in terms of performance shall be done through RTL simulation and FPGA-based circuit emulation, and in terms of ASIC circuit area and power consumption through gate-level synthesis and switching activity simulation. The available tools and technology library for these tasks are Synopsys Design Compiler, Synopsys PrimeTime and Mentor ModelSim with an 65 nm low-voltage low-power ASIC standard cell technology by UMC.


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