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Logo: Institute of Microelectronic Systems
Logo Leibniz Universität Hannover
Logo: Institute of Microelectronic Systems
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Tensilica Day 2016

Cadence Design Systems and the Institute of Microelectronic Systems have invited to the first TensilicaDay on 9th February 2016. Theme for the workshop are Tensilica processors with application-specific instruction-set extensions (ASIPs) in actual research.

In the morning, Marcus Binning, Tensilica Senior AE Manager, has hosted two expert-level tutorials detailing the Tensilica Instruction Extension Language (TIE Language). In the afternoon experts from university and industry have presented current trends in ASIP design.

During the lunch break, there was the opportunity to observe various ASIP demonstrators.

The agenda of the workshop can be found here .

Session 1 - Tensilica Tutorials

Anton Klotz: Extending the Cadence Ecosystem in Academic World  pdf

Marcus Binning: What can the TIE Language do for you?  pdf

Marcus Binning: Xtensa + TIE Feature Update - up to Release FR.3  pdf

Session on ASIP-Case Studies I

Michael Gautschi: Tensilica at ETHZ: Accelerating Function Kernels for Elliptic Curve Operations and Mobile Communication Algorithms  pdf

Nico Mentzer: Analyzing the Performance-Hardware Trade-off of ASIP-based Image Feature Extraction

Michael Hübner: Run Time Adaptive Processor Architectures  pdf

Juan Fernando Eusse: A flexible ASIP architecture for connected components labeling: Implementation, Lessons Learned, and Integration into Novel Design Tools   pdf

Session on ASIP-Case Studies II

Jens Benndorf: Heterogeneous Multi-Core Architecture for Image Sensor Processing featuring Tensilica Cores  pdf

Guillermo Payá Vayá: rASP - Reconfigurable Application Specific Processors Challenges and Opportunities pdf

Sebastian Haas: An MPSoC for Energy-Efficient Query Processing  pdf