Tensilica Day 2019
Cadence Design Systems and the Institute of Microelectronic Systems invite to the fourth Tensilica Day on 23rd - 24th September 2019. The theme for the workshop are processors with an application-specific instruction-set extension (ASIP) in current academic and industrial research. Due to the high interest, the workshop is extended to one and a half day in 2019.
The workshop starts with a tutorial by Cadence Designs Systems, about how to extend Tensilica processors with customized instructions. Subsequent, experts from university and industry present current trends in ASIP design. During the lunch break, there is the opportunity to have a look at various hardware demonstrators. Additionally, the Protium FPGA prototyping platform is presented with an emulation of the Tensilica IVP DSP and a camera-based pedestrian detection algorithm. A main topic of this years Tensilica Day are HW-Design, SW-Tools and their Co-Design for Deep Learning ASIPs.
This years Tensilica Day 2019 will be hosted in the "Royal Horse Stable" of the Leibniz University Hannover, Appelstr. 7, 30167 Hannover. Sufficient parking facilities are available in the immediate vicinity.
Please register, free of cost, under this link
Agenda Day 1 (23. September 2019)
Welcome & Introduction
Tensilica 2019. What’s New?
Session 1 Neural Network Acceleration
Configurable Processing Elements for Flexible Acceleration of Variable Precision Neural Networks
CNN Inference on Coarse-Grain Reconfigurable Arrays under Throughput Constraints.
A Power Efficient Network Coding Accelerator
Session 2 Theory & Software Tooling
Exploration of Memory Energy-Reduction Strategies for a Deep Learning ASIP
Evaluation and optimization of a Tensilica processor for hearing aids
Welcome Reception & Networking (18:00-20:00)
Agenda Day 2 (24. September 2019)
Welcome & Introduction 9:00
Session 3 Industrial ASIP Applications
New general purpose FPGA with novel architecture
Structure from motion on Tensilica Vison P6
A unified visual computing platform
Lunch and Trends
Next Generation Neuro Science Simulation Systems
Session 4 ASIP Case-Studies I
Towards more adaptive accelerators: An approach utilizing the Tensilica LX7 ASIP
InterSloth: Global Hardware-Based Scheduling in a Multi-Core RTOS on RISC-V
Energy Efficient GFDM Accelerator for Users Devices
Session 5 ASIP Case-Studies II
Application Specific Memory Controller
Application-Specific Soft-Core Vector Processor for Advanced Driver
The agenda of the workshop can be downloaded here.
Tensilica Day History
Information about the Tensilica Day 2018 can be found here.
Information about the Tensilica Day 2017 can be found here.
Information about the Tensilica Day 2016 can be found here.