Verification, Validation and Testing of ASIC Designs
The students will learn techniques for verification, validation and testing of ASIC designs. Based on practical examples and up-to-date development tools, the students are introduced to challenges of today's chip development and testing.
This lecture is new for winter semester 2019/20.
Therefore, this website will be updated on a regular basis.
Start: Winter semester 2019/20
Extent: 2 lecture hours + 1 exercise hour + 1 project hour (5 CP)
Tue, 09:30 - 11:00
Room 335, Building 3703: Technische Informatik
Tue, 11:15 - 12:45
Room 335,Building 3703: Technische Informatik
Recommended prior knowledge
This lecture is held in English.
It is designed for master course students.
The first 7 exercise lessons will consist of a introduction to SystemC. The rest of the semester is designated to a self-organized project.
Contact for further inquiries
- Introduction to Verification, Validation and Testing
- SoC Verification
- Verification Challenges
- Approaches to Verification (Formal Verification, Equivalence Checking, Model Checking, Functional Verification, Testbench Generation)
- Functional Verification and Coverage (Verification Metrics)
- Verificication Plan
- Design for Reuse
- SoC Validation
- Validation Challenges
- Test Generation (Different Approaches)
- SoC Testing
- Testing Challenges
- Digital Test Architectures (Digital Logic, Memory, ...)
- System Test Architectures (incl. self-testing)
- Low-Power Testing
- Design for Debug and Diagnossis
More information can be found in StudIP.