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Logo: Institute of Microelectronic Systems
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Logo: Institute of Microelectronic Systems
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Verification, Validation and Testing of ASIC Designs

apl.-Prof. Dr.-Ing. Guillermo Payá Vayá

The students will learn techniques for verification, validation and testing of ASIC designs. Based on practical examples and up-to-date development tools, the students are introduced to challenges of today's chip development and testing.

This lecture is new for winter semester 2019/20.
Therefore, this website will be updated on a regular basis.

Lectures

Start: Winter semester 2019/20
Extent: 2 lecture hours + 2 exercise hours (5 CP)

Dates:
(to be determined)

Exercises

Dates:
(to be determined)

Exam

Oral examination.

Recommended prior knowledge

Please note

This lecture is held in English.
It is designed for master course students.

Contact for further inquiries

apl.-Prof. Dr.-Ing. Guillermo Payá Vayá

Inhaltsverzeichnis

  • Introduction to Verification, Validation and Testing
  • SoC Verification

    • Verification Challenges
    • Approaches to Verification (Formal Verification, Equivalence Checking, Model Checking, Functional Verification, Testbench Generation)
    • Functional Verification and Coverage (Verification Metrics)
    • Verificication Plan
    • Design for Reuse

  • SoC Validation

    • Validation Challenges
    • Test Generation (Different Approaches)

  • SoC Testing

    • Testing Challenges
    • Digital Test Architectures (Digital Logic, Memory, ...)
    • System Test Architectures (incl. self-testing)
    • Low-Power Testing
    • Design for Debug and Diagnossis

More information can be found in StudIP.