Forschung
Publikationen Architekturen und Systeme

Publikationen des Fachgebiets Architekturen und Systeme

Konferenzbeiträge

  • Stanislawski, N.; Cholewa, F.; Heymann, H.; Kraus, X.; Heene, S.; Witt, M.; Thoms, S.; Blume, C.; Blume, H. (2020): Automated Bioreactor System for the Cultivation of Autologous Tissue-Engineered Vascular Grafts2020 42nd Annual International Conference of the IEEE Engineering in Medicine Biology Society (EMBC) Weitere Informationen
    DOI: 10.1109/EMBC44109.2020.9175340
  • Wahalla, M.; Paya-Vaya, G.; Blume H. (2020): CereBridge: An Efficient, FPGA-based Real-Time Processing Platform for True Mobile Brain-Computer Interfaces42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC) Weitere Informationen
    DOI: 10.1109/EMBC44109.2020.9175623
  • Weißbrich, M.; García-Ortiz, A.; Payá-Vayá, G. (2020): A Runtime-Configurable Operand Masking Technique for Energy-Efficient Approximate Processor Architectures2020 International Conference on Modern Circuit and Systems Technologies (MOCAST 2020, accepted for publication)
  • Karrenbauer, J.; Gerlach, L.; Payá-Vayá, G.; Blume, H. (2020): Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing AidsInternational Conference on Modern Circuits and Systems Technologies (MOCAST) on Electronics and Communications (accepted for publication)
  • Gerlach, L.; Stuckmann, F.; Blume, H.; Payá-Vayá, G. (2020): Issue-Slot Based Predication Encoding Technique for VLIW ProcessorsInternational Conference on Modern Circuits and Systems Technologies (MOCAST) on Electronics and Communications (accepted for publication)
  • Weißbrich, M.; Roskamp, S.; Webering, F.; Blume, H.; Payá-Vayá, G. (2020): Improving the Performance of a High-Temperature DSP Using Circuit-Level Timing SpeculationCadenceLIVE Europe 2020 (accepted for presentation)
  • Behmann, N.; Cheng, Y.; Schleusner, J.; Blume, H. (2019): Probabilistic 3D Point Cloud Fusion on Graphics Processors for Automotive (Poster)2019 22nd International Conference on Information Fusion (FUSION), Ottawa
  • Schleusner, J.; Neu, L.; Behmann, N.; Blume, H. (2019): Deep Learning Based Classification of Pedestrian Vulnerability Trained on Synthetic Datasets2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)
    ISBN: 978-1-7281-2745-3
  • Karrenbauer, J.;Gerlach, L.;Payá-Vayá, G.;Blume, H. (2019): Evaluation and Optimization of a Tensilica Processor for Hearing AidsTensilica Day 2019, Hannover
  • Blume, H.; Payá-Vayá, G.; Gerlach, L. (2019): KAVUAKA: A low power application specific hearing aid processor53rd Annual Conference of the German Society for Biomedical Engineering Weitere Informationen
  • Lüders, M.; Arndt, O. J.; Blume, H. (2019): Multicore Performance Prediction – Comparing Three Recent Approaches in a Case StudyIntl. Workshop Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'2019), hosted at Intl. European Conf. Parallel and Distributed Computing (Euro-Par 2019) Weitere Informationen
    DOI: 10.1007/978-3-030-48340-1_22
    ISBN: 978-3-030-48339-5
  • Gerlach, L.; Payá-Vayá, G.; Blume, H. (2019): KAVUAKA: A Low Power Application Specific Hearing Aid Processor27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Cuzco, Perú
    DOI: 10.1109/VLSI-SoC.2019.8920354
  • Karrenbauer, J.;Gerlach, L.;Payá-Vayá, G.;Blume, H. (2019): Automated Design Space Exploration of Digital Audio Processors for Hearing AidsCDNLive 2019, Munich
  • Arndt, O. J.; Lüders, M.; Blume, H. (2019): Statistical Performance Prediction for Multicore Applications Based on Scalability CharacteristicsIntl. Conf. Application-specific Systems, Architectures and Processors (ASAP 2019), IEEE
    DOI: 10.1109/ASAP.2019.00015
  • Gesper, S.; Weißbrich, M., Nolting, S.; Stuckenberg, T.; Jääskeläinen, P.; Blume, H.; Payá-Vayá, G. (2019): Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh EnvironmentsEmbedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019 International Conference on, Springer LNCS, Pythagorion, Greece (accepted)
  • Stuckenberg, T.; Gottschlich, M.; Nolting, S.; Blume, H. (2019): Design and Optimization of an ARM Cortex-M based SoC for TCP/IP Communication in High Temperature ApplicationsEmbedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Springer LNCS (accepted)
  • Behmann, N.; Blume, H. (2019): Real-Time LED Flicker Mitigation on a Tensilica Vision DSP for Digital Side Mirror SystemsCadence User Conference (CDNLive EMEA 2019), München, Germany
  • Behmann, N.; Payá Vayá, G.; Blume, H. (2019): CNN Design Space Exploration on Tensilica Vision P6 DSPCadence User Conference (CDNLive EMEA 2019), München, Germany
  • Rother, N.; Webering, F.; John C.; Rahlf, A.; Hamacher, D.; Zech, A.; Blume, H. (2019): Verwendung von Intertialsensoren zur automatisierten Auswertung sensomotorischer Tests6. Ambient Medicine Forum
    ISBN: 973-3-7369-9961-9
  • Behmann, N.; Payá Vayá, G.; Blume, H. (2019): Design Space Exploration for Convolutional Neural Networks on a 22 nm FD-SOI SoCEmbedded World Conference (ewc), Nürnberg
  • Nolting, S.; Gesper, S.; Schmider, A.; Weißbrich, M.; Stuckenberg, T.;Blume, H.; Paya-Vaya, G. (2018): Processor Architecture Tradeoffs for On-Site Electronics in Harsh EnvironmentsCDNLive 2018, Munich
  • Rother, N.; Stuckenberg T.; Nolting S.; Uhlemann C.; Blume H. (2018): A Case Study on Multi-Softcore Aided Hardware Architectures for Powerline MAC-LayerICT.OPEN 2018 (Published)
  • Spindeldreier, C. and Bartosch, W. and Wendrich, T. and Rasel, E. M. and Ertmer, W. and Blume, H. (2018): FPGA based Laser Frequency Stabilization using FM-SpectroscopySPIE LASE 2018, Laser Resonators, Microresonators, and Beam Control XX, San Francisco, CA, United States
    DOI: 10.1117/12.2288370
  • Dürre, J.; Paradzik, D.; Blume. H. (2018): A HOG-based real-time and multi-scale Pedestrian Detector Demonstration System on FPGA26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, CA, USA
  • Wörner, L.; Jens Grosse, J.; Warner, M.; Schubert, C.; Becker, D.; Frye, K.; Herr, W.; Wendrich, T.; Gaaloul, N.; Spindeldreier, C.; Meister, M.; Wenzlawski, A.; Marburger, J.-P.; Krutzik, M.; Henderson, V.; Bawamia, A. I.; Herrmann, S.; Müntinga, H.; Sommer, J.; Prat, A.; Peters, A.; Wicht, A.; Lüdtke, D.; Windpassiger, P.; Blume, H.; Rasel, E. M.; Schleich, W.; Braxmaier, C. (2018): Quantum Gases aboard the ISS - Capabilities of the BECCAL Project69th International Astronautical Congress (IAC 2018), Bremen, Germany Weitere Informationen
  • Behmann, N.; Blume, H. (2018): Real-Time LED Flicker Detection and Mitigation: Architecture and FPGA-ImplementationIEEE International Conference on Electronics (ICECS), Berlin
  • Behmann, N.; Mehltretter, M.; Kleinschmidt, S. P.; Wagner, B.; Heipke, C.; Blume, H. (2018): GPU-enhanced Multimodal Dense MatchingIEEE Nordic Circuits and Systems Conference (NORCAS), Tallinn
  • Jaaskelainen, P.; Tervo, A.; Paya Vaya, G.; Viitanen, T.; Behmann, N.; Takala, J.; Blume, H. (2018): Transport-Triggered Soft CoresIEEE Intl. Parallel and Distributed Processing Symposium
  • Behmann, N.; Schewior, G..; Hesselbarth, S.; Blume, H. (2018): Selective LED Flicker Detection and Mitigation Algorithm for Non-HDR Video SequencesIEEE Intl. Conf. on Consumer Electronics, Berlin
  • Herzke, T.; Kayser, H.; Seifert, C.; Maanen, P.; Obbard, C.; Payá-Vayá, G.; Blume, H.; Hohmann, V. (2018): Open Hardware Multichannel Sound Interface for Hearing Aid Research on BeagleBone Black with openMHA: Cape4allProceedings of the Linux Audio Conference 2018
    DOI: 10.14279/depositonce-7046
  • Weißbrich, M.; Najafi, A.; García-Ortiz, A.; Payá Vayá, G. (2018): ATE-Accuracy Trade-Offs for Approximate Adders and Multipliers in Pipelined Processor Datapaths2018 Third Workshop on Approximate Computing (AxC18, www.lirmm.fr/axc18)
  • Stuckenberg, T.; Blume, H. (2017): A Hardware Efficient Preamble Detection Algorithm for Powerline CommunicationJournal of Communications, JCM
    DOI: 10.12720/jcm
  • Najafi, A.; Weißbrich, M.; Payá Vayá, G.; García-Ortiz, A. (2017): A Fair Comparison of Adders in Stochastic Regime2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
  • Hartig, J.; Payá Vayá, G.; Heymann, H.; Blume, H. (2017): Tool-Supported Design Space Exploration of a Processor System for SIFT-Feature DetectionIEEE International Conference on Consumer Electronics (ICCE), Berlin, 2017
    DOI: 10.1109/ICCE-Berlin.2017.8210619
  • Leibold, C.; Stanislawski, N.; Blume, C.; Blume, H. (2017): A Mobile Electrochemical (Bio-)Sensor Node for a Vascular Graft BioreactorBiomedical Circuits and Systems Conference (BioCAS) 2017
  • Wielage, M.; Cholewa, F.; Fahnemann, C.; Pirsch, P.; Blume, H. (2017): High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized BackprojectionProceedings of CANDAR Symposium (2017)
  • Wielage, M.; Cholewa, F.; Riggers, C.; Pirsch, P.; Blume, H. (2017): Parallelization Strategies for Fast Factorized Backprojection SAR on Embedded Multi-Core Architectures2017 IEEE International Conference on Microwave, Communications, Antennas and Electronic Systems
  • Cholewa, F.; Wielage M.; Pirsch, P.; Blume, H. (2017): Synthetic Aperture Radar with Fast Factorized Backprojection: A Scalable, Platform Independent Architecture for Exhaustive FPGA Resource UtilizationInternational Conference on Radar Systems 2017 (RADAR)
  • Nolting, S.; Giesemann, F.; Hartig, J.; Schmider, A.; Payá-Vayá, G (2017): Application-Specific Soft-Core Vector Processor for Advanced Driver Assistance Systems27th International Conference on Field-Programmable Logic and Applications 2017, Ghent, Belgium
  • Nolting, S.; Liu, L.; Payá-Vayá, G. (2017): Two-LUT-Based Synthesizable Temperature Sensor for Virtex-6 FPGA Devices27th International Conference on Field-Programmable Logic and Applications 2017, Ghent, Belgium
  • Weißbrich, M.; Payá-Vayá, G.; Gerlach, L.; Blume, H.; Najafi, A.; García-Ortiz, A. (2017): FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
    DOI: 10.1109/PATMOS.2017.8106956
  • Dürre, J.; Blume, H. (2017): Teaching VHDL Design to Schoolchildren – A Scalable and Flexible FPGA FrameworkCadence User Conference (CDNLive EMEA 2017), München, Germany
  • Dürre, J.; Blume, H. (2017): SF3: A Scalabe and Flexible FPGA-Framework for Education and Rapid Prototyping, Proceedings of the International Conference on Microelectronic Systems Education (MSE 2017), Lake Louise, Canada
  • Hartig, J.; Payá Vayá, G.; Mentzer, N.; Blume, H. (2017): Balanced Application-Specific Processor System for Efficient SIFT-Feature DetectionIEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVII), Stamatis Vassiliadis Best Paper Award, 2017
    DOI: 10.1109/SAMOS.2017.8344614
  • Giesemann, F.; Payá-Vayá, G.; Gerlach, L.; Blume, H.; Pflug, F.; von Voigt, G. (2017): Using a Genetic Algorithm Approach to Reduce Register File Pressure during Instruction SchedulingInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation 2017 (SAMOS XVII)
    DOI: 10.1109/SAMOS.2017.8344626
  • Gerlach, L.; Marquardt, D.; Payá Vayá, G.; Liu, S.; Weißbrich, M.; Doclo, S.; Blume, H. (2017): Analyzing the Trade-Off between Power Consumption and Beamforming Algorithm Performance using a Hearing Aid ASIPEmbedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2017 International Conference on, IEEE, Pythagorion, Greece Weitere Informationen
    DOI: 10.1109/SAMOS.2017.8344615
  • Webering, F.; Payá-Vayá, G.; Aditya, E.; Dürre, J.; Blume, H. (2017): An Integrated Heated Testbench for Characterizing High Temperature ICs [Best Flash Presentation Award]ICT.OPEN2017, Amersfoort, Netherlands
  • Arndt, O. J.; Spindeldreier, C.; Wohnrade, K.; Pfefferkorn, D.; Neuenhahn, M.; Blume, H. (2017): FPGA Accelerated NoC-Simulation – A Case Study on the Intel Xeon Phi Ringbus TopologyIntl. Symp. Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017), ACM
    DOI: 10.1145/3120895.3120916
  • Seifert, C.; Thiemann, J.; Gerlach, L.; Volkmar, T.; Payá-Vayá, G.; Blume, H.; van de Par, S. (2017): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a VLIW-SIMD ProcessorInternational Conference on Multimedia and Expo (ICME) 2017, IEEE
    DOI: 10.1109/ICME.2017.8019478
  • Arndt, O. J.; Träger, F. D.; Moß, T.; Blume, H. (2017): Portable Implementation of Advanced Driver-Assistance Algorithms on Heterogeneous ArchitecturesHeterogeneity in Computing Workshop (HCW-17), hosted at Intl. Parallel and Distributed Processing Symp. Workshops (IPDPSW 2017), IEEE
    DOI: 10.1109/IPDPSW.2017.100
  • Behmann, N.; Blume, H. (2017): Object Detection for Mobile and Automotive - Convolutional Neural Networks (CNNs) on Tensilica Vision DSPsCadence User Conference (CDNLive EMEA 2017), München, Germany
  • Meyer, B. T.; Mallidi, S. H.; Castro Martínez, A. M.; Payá-Vayá, G.; Kayser, H.; Hermansky, H. (2016): Performance Monitoring for Automatic Speech Recognition in Noisy Multi-Channel Environments2016 IEEE Spoken Language Technology Workshop (SLT)
    DOI: 10.1109/SLT.2016.7846244
  • Cholewa, F.: Wielage, M.; Pirsch, P.; Blume, H. (2016): An FPGA Architecture for Velocity Independent Backprojection in FMCW-based SAR SystemsThe 16th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT2016)
  • Behmann, N.; Seifert, C.; Payá Vayá, G.; Blume, H.; Jääskeläinen, P.; Multanen, J.; Kultala, H.; Takala, J.; Thiemann, J.; van de Par, S. (2016): Customized High Performance Low Power Processor for Binaural Speaker LocalizationInternational Conference on Electronics, Circuits and Systems (ICECS 2016), IEEE
  • Meinl, F.; Kunert, M.; Blume, H. (2016): Hardware Acceleration of Maximum-Likelihood Angle Estimation for Automotive MIMO RadarsConference on Design & Architectures for Signal & Image Processing (DASIP), 2016 (accepted for publication)
  • Nolting, S.; Payá Vayá, G.; Giesemann, F.; Blume, H. (2016): Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
    DOI: 10.1109/IPDPSW.2016.158
  • Baydakov, K.; Roskamp, S.; Wohnrade, K.; Dürre, J.; Blume, H. (2016): A Scalable Architecture for Low-Latency Network-Encryption in Low-Power DevicesPoster-Session at the 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland
  • Rath, J.; Dürre, J.; Blume, H. (2016): A General Purpose FPGA-Accelerator with Standard USB 3.0 InterfacePoster-Session at the 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland
  • Gerlach, L.; Payá Vayá, G.; Blume, H. (2016): Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors2016 IEEE International Workshop on Signal Processing Systems (SiPS), Dallas, United States Weitere Informationen
    DOI: 10.1109/SiPS.2016.52
  • C. Leibold, J. Wilkening, C. Blume, H. Blume (2016): A Toolchain for the 3D-Visualization of Bioartificial Vascular Grafts based on Ultrasound Images Biomedical Circuits and Systems Conference (BioCAS) 2016
  • Dürre, J.; Payá Vayá, G.; Blume, H. (2016): Teaching Digital Logic Circuit Design via Experiment-Based Learning - Print your own Logic CircuitProceedings of the 20th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2016), Orlando, USA
  • Spindeldreier, C.; Wendrich, T.; Rasel, E. M.; Ertmer, W.; Blume, H. (2016): FPGA-based Frequency Estimation of a DFB laser using Rb Spectroscopy for Space MissionsInternational Conference on Application-specific Systems, Architectures and Processors (ASAP 2016), IEEE
    DOI: 10.1109/ASAP.2016.7760795
    ISBN: 978-1-5090-1503-0
  • Wielage, M.; Cholewa, F.;Pirsch, P.;Blume, H. (2016): Experimental violation of the Start-Stop-Approximation using a Holistic Rail-based UWB FMCW-SAR System11th European Conference on Synthetic Aperture Radar (EUSAR 2016)
  • Gerlach, L.; Payá-Vayá, G.; Blume, H. (2016): A Low Latency Multichannel Audio Interface for Low Power SIMD Digital Signal ProcessorsICT.OPEN2016, Amersfoort, Netherlands
    ISBN: 978-90-73461-932
  • Nowosielski, R.; Gerlach, L.; Bieband, S.; Payá-Vayá, G.; Blume, H. (2015): FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC DesignProceedings of Design, Automation & Test in Europe (DATE2015), Grenoble, France
    ISBN: 978-3-9815-3704-8
  • Meinl, F.; Schubert, E.; Kunert, M.; Blume, H. (2015): Realtime FPGA-based processing unit for a high-resolution automotive MIMO radar platformEuropean Radar Conference (EuRAD), 2015
    DOI: 10.1109/EuRAD.2015.7346275
    ISBN: 978-2-8748-7041-5
  • Meinl, F.; Schubert, E.; Kunert, M.; Blume, H. (2015): Realtime FPGA-based Processing Unit for a High-Resolution Automotive MIMO Radar PlatformProceedings of the European Microwave Week (EuMW 2015), Paris, 6.-11.9.2015
  • Kock, M.; Busch, S.; Blume, H. (2015): Hardware Accelerator for Minimum Mean Square Error Interference AlignmentIEEE DSP 2015
  • Seifert, C.; Payá-Vayá, G.; Blume, H.;Herzke, T.;Hohmann, V. (2015): A Mobile SoC-Based Platform for Evaluating Hearing Aid Algorithms and ArchitecturesConsumer Electronics - Berlin (ICCE-Berlin), 2015 5th IEEE International Conference on
  • Arndt, O. J.; Linde, T.; Blume, H. (2015): Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU ArchitectureGlobal Conf. Signal & Information Processing (GlobalSIP 2015), IEEE
    DOI: 10.1109/GlobalSIP.2015.7418429
  • Hesselbarth, S.;Schewior, G.;Blume, H. (2015): Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA EmulationDesign and Architectures for Signal and Image Processing (DASIP), 2015 Conference on
    ISBN: 978-1-4673-7738-6
  • Gerlach, L.; Payá Vayá, G.; Blume, H. (2015): An Area Efficient Real- and Complex-Valued Multiply-Accumulate SIMD Unit for Digital Signal Processors2015 IEEE Workshop on Signal Processing Systems, Hangzhou, China Weitere Informationen
    DOI: 10.1109/SiPS.2015.7345019
  • Arndt, O. J.; Lefherz, T.; Blume, H (2015): Abstracting Parallel Programming and its Analysis Towards Framework Independent DevelopmentIntl. Symp. Embedded Multicore/Many-Core Systems-on-Chip (MCSoC-15), IEEE
    DOI: 10.1109/MCSoC.2015.22
  • Pfefferkorn, Daniel; Schmider, Achim; Payá Vayá, Guillermo ; Neuenhahn, Martin; Blume, Holger (2015): FNOCEE: A Framework for NoC Evaluation by FPGA-based EmulationSAMOS 2015
    DOI: 10.1109/SAMOS.2015.7363663
  • Pfefferkorn, Daniel ; Jeschke, Hartwig; Blume, Holger (2015): Energy- and Latency-Aware Simulation of Battery-Operated Wireless Embedded Networks for Home AutomationProceedings SIES 2015
    DOI: 10.1109/SIES.2015.7185050
  • Behmann, N.; Arndt, O. J.; Blume, H. (2015): Parallel Implementation of Real-Time Block-Matching based Motion Estimation on Embedded Multi-Core ArchitecturesICT.OPEN 2015
  • Nolting, S.; Payá-Vayá, G.; Giesemann, F.; Blume, H. (2015): Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture11th International Symposium on Applied Reconfigurable Computing (ARC 2015)
  • Nowosielski, R.; Hartig, J.; Payá-Vayá, G.; Blume, H.; Garcia-Ortiz, A. (2015): Exploring Different Approximate Adder Architecture Implementations in a 250°C SOI Technology1st Workshop On Approximate Computing (WAPCO), HiPEAC 2015 Weitere Informationen
  • Bartels, C.; Zhang, C.; Payá-Vayá, G.; Blume, H. (2015): A Synthesizable Temperature Sensor on FPGA using DSP-Slices for Reduced Calibration Overhead and Improved StabilityArchitecture of Computing Systems (ARCS 2015), Best Paper Award
    ISBN: ISBN 978-3-319-16086-3
  • Cholewa, F.; Pfitzner, M.; Fahnemann, C.; Pirsch, P.; Blume, H. (2014): Synthetic Aperture Radar with Backprojection: A Scalable, Platform Independent Architecture for Exhaustive FPGA Resource UtilizationInternational Radar Conference 2014 (RADAR)
  • Hartig, J.; Gerlach, L.; Payá-Vayá, G.; Blume, H. (2014): Customizing a VLIW-SIMD Application-Specific Instruction-Set Processor for Hearing Aid DevicesIEEE International Workshop on Signal Processing Systems 2014 (SiPS), Belfast, UK
    DOI: 10.1109/SiPS.2014.6986072
  • Schewior, G.; Zahl, C.; Blume, H.; Wonneberger, S.; Effertz, J. (2014): HLS-based FPGA Implementation of a Predictive Block-based Motion Estimation Algorithm - A Field ReportDesign and Architectures for Signal and Image Processing (DASIP), 2014 Conference on
    DOI: 10.1109/DASIP.2014.7115633
    ISBN: 979-10-92279-05-4
  • Dellavale, D.; Kock, M.; Blume, H.; Alam, M.; Schwabe, K.; Krauss, J. K. (2014): Implementation of Phase-to-Amplitude Coupling Analysis Algorithms in Deep Brain Stimulation DevicesDGBMT 2014
  • Hesselbarth, S.; Baumgart, T.; Blume, H. (2014): Hardware-assisted Power Estimation for Design-stage Processors using FPGA Emulation24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014
    DOI: 10.1109/PATMOS.2014.6951877
  • Meinl, F.; Kunert, M.; Blume, H. (2014): Massively Parallel Signal Processing Challenges within a Driver Assistant Prototype Framework - First Case Study Results with a Novel MIMO-RadarInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV) (2014)
    DOI: 10.1109/SAMOS.2014.6893232
  • Arndt, O. J.; Becker, D.; Giesemann, F.; Payá Vayá, G.; Bartels, C.; Blume, H. (2014): Performance Evaluation of the Intel Xeon Phi Manycore Architecture Using Parallel Video-Based Driver Assistance AlgorithmsIntl. Conf. Embedded Computer Systems (SAMOS XIV), IEEE (125 - 132)
    DOI: 10.1109/SAMOS.2014.6893203
  • Giesemann, F.; Paya Vaya, G.; Blume, H.; Limmer, M.; Ritter, W. (2014): A Comprehensive ASIC/FPGA Prototyping Environment for Exploring Embedded Processing Systems for Advanced Driver Assistance ApplicationsInternational Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS), 2014
  • Fenzi, M.; Mentzer, N.; Payá Vayá, G.; Nguyen, T.; Risse, T.; Blume, H.; Ostermann, J.; (2014): Automatic Situation Assessment for Event-driven Video AnalysisProceedings of 11th IEEE International Conference on Advanced Video and Signal-Based Surveillance (2014)
    DOI: 10.1109/AVSS.2014.6918641
  • Mentzer, N.; Payá Vayá, G.; Blume, H.; von Egloffstein, N.; Ritter, W. (2014): Instruction-Set Extension for an ASIP-based SIFT Feature ExtractionProceedings of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
    DOI: 10.1109/SAMOS.2014.6893230
  • Schmädecke, I.; Blume, H. (2014): Design Space Exploration of Hardware Architectures (accepted for publication) for Content Based Music Classification32nd INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS 2014 (ICCE)
  • Brückner, H.-P.; Theimer, W.; Blume, H. (2014): Real-Time Low Latency Movement Sonification in Stroke Rehabilitation Based on a Mobile PlatformConsumer Electronics (ICCE), 2014 IEEE International Conference on, (264-265)
    DOI: 10.1109/ICCE.2014.6775997
    ISBN: 978-1-4799-1290-2
  • Brückner, H.-P.; Spindeldreier, C.; Blume, H. (2014): Design and Evaluation of a Hardware-Accelerator for Energy Efficient Inertial Sensor Fusion on Heterogeneous SoC ArchitecturesThe 15th International Conference on Biomedical Engineering IFMBE Proceedings, 43, Goh, James, Springer International Publishing (227-230)
    DOI: 10.1007/978-3-319-02913-9_58
    ISBN: 978-3-319-02912-2
  • Winter, L.; Alam, M.; Schwabe, K.; Heissler, H.; Delavalle, D.; Blume, H.; Lütjens, G.; Kahl, K.; Krauss, K. (2014): Neuronal activity in the bed nucleus of the stria terminalis/ internal capsule in OCD in response to neutral and aversive stimuli (accepted for publication)65.Jahrestagung der Deutsche Gesellschaft für Neurochirurgie (DGNC)
  • Wielage, M.; Blume, H. (2014): The Use of the LEON2 Microprocessor as a Control Instance for Real-Time SAR Image ProcessingSynthetic Aperture Radar, 2014. EUSAR. 10th European Conference
    ISBN: 978-3-8007-3607-2
  • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2013): FPGA-based Architecture for real-time SAR processing with integrated Motion CompensationThe 4th Asia-Pacific Conference on Synthetic Aperture Radar (APSAR)
  • Brückner, H.-P.; Spindeldreier, C.; Blume, H. (2013): Modification and fixed-point analysis of a Kalman filter for orientation estimation based on 9D inertial measurement unit dataEngineering in Medicine and Biology Society (EMBC), 2013 35th Annual International Conference of the IEEE, (3953-3956)
    DOI: 10.1109/EMBC.2013.6610410
    ISBN: 1557-170X
  • Kock, M.; Blume, H. (2013): Effiziente Hardwarearchitekturen für Interference Alignment in drahtlosen Kommunikationssystemen15. ITG-Fachtagung für Elektronische Medien (Fernsehsehminar)
  • Schmädecke, I.; Leibold, C.; Brückner, H.-P.; Blume, H. (2013): Project-organized Education: From FPGA Prototyping to ASIC DesignMicroelectronic Systems Education (MSE), 2013 IEEE International Conference on, (9-12)
    DOI: 10.1109/MSE.2013.6566691
    ISBN: 978-1-4799-0139-5
  • Hesselbarth; Blume, S.; Holger (2013): Methoden zur applikationsspezifischen Verlustleitungsoptimierung für eingebettete Prozessoren15. ITG-Fachtagung für Elektronische Medien (Fernsehsehminar), Informationstechnische Gesellschaft im VDE Weitere Informationen
  • Schmädecke, I.; Blume, H. (2013): High Performance Hardware Architectures for Automated Music ClassificationAlgorithms from and for Nature and Life, Springer (539-547)
    DOI: 10.1007/978-3-319-00035-0_55
    ISBN: 978-3-319-00034-3
  • Brückner, H.-P.; Spindeldreier, C.; Blume, H. (2013): Energy-Efficient Inertial Sensor Fusion on Heterogeneous FPGA-Fabric / RISC System on ChipSensing Technology (ICST), 2013 Seventh International Conference on, (506-511)
    DOI: 10.1109/ICSensT.2013.6727704
    ISBN: 978-1-4673-5220-8
  • Schmädecke, I.; Blume, H. (2013): Hardware-Accelerator Design for Energy-Efficient Acoustic Feature Extraction (accepted for publication)2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)
  • Brückner, H.-P.; Blume, H. (2013): Analysis of Multiple Hardware Platforms for Power-Efficient, Low-Latency Interactive Movement Sonification in Stroke-RehabilitationProceedings of 1st Russian-German Conference on Biomedical Engineering, Hannover, B. Chichkoc, E. Fadeeva, L.A. Kahr, T. Ortmaier, PZH Verlag (83)
    ISBN: 978-3-944586-25-0
  • Brückner, H.-P.; Blume, H. (2013): Comparison of Hardware Platforms for Low-Power, Real-Time Interactive Movement SonificationMultisensory Motor Behavior: Impact of Sound, International Conference Weitere Informationen
  • Schewior, G.; Blume, H. (2013): Enhanced Motion Estimation for Driver Assistance Systems - Integration of a Curved Road ModelConsumer Electronics (GCCE), 2013 IEEE 2nd Global Conference on, (483-487)
    DOI: 10.1109/GCCE.2013.6664897
    ISBN: 978-1-4799-0890-5
  • Brückner, H.-P.; Nowosielski, R.; Kluge, H.; Blume, H. (2013): Mobile and Wireless Inertial Sensor Platform for Motion Capturing in Stroke Rehabilitation SessionsAdvances in Sensors and Interfaces (IWASI), 2013 5th IEEE International Workshop on, (14-19)
    DOI: 10.1109/IWASI.2013.6576085
    ISBN: 978-1-4799-0039-8
  • Payá-Vayá, G.; Seifert, C.; Blume, H. (2013): Design of Application-Specific Instruction-Set Processors for Digital Hearing Aid Systems1st Russian German Conference on Biomedical Engineering (RGC 2013), Proceedings of 1st Russian German Conference on Biomedical Engineering (RGC 2013), B. Chichkov, E. Fadeeva, L.A. Kahrs, T. Ortmaier, PZH Verlag (32)
    ISBN: 978-3-944586-25-0
  • Nowosielski, R.; Gerlach, L.; Payá-Vayá, G.; Hesselbarth, S.; Blume, H. (2013): Methodology for Observation and Evaluation of Fault Tolerance Implementations inside High Temperature ASICsConference ICT.OPEN 2013, Proceedings of ICT.OPEN 2013, (97--101), Eindhoven, Netherlands Weitere Informationen
    ISBN: 978-90-73461-84-0
  • Dellavale, D.; Leibold, C.; Payá-Vayá, G.; Blume, H.; Alam, M.; Schwabe, K.; Krauss, J. (2013): Optimization of a Phase–to–Amplitude Coupling Algorithm for Real–Time Processing of Brain Electrical SignalsConference ICT.OPEN 2013, Proceedigns of ICT.OPEN 2013, (68--73) Weitere Informationen
    ISBN: 978-90-73461-84-0
  • Werner, N.; Payá-Vayá, G.; Blume, H. (2013): Case Study: Using the Xtensa LX4 Configurable Processor for Hearing Aid ApplicationsConference ICT.OPEN 2013, Proceedings of ICT.OPEN 2013, (27-32) Weitere Informationen
    ISBN: 978-90-73461-84-0
  • Seifert, C.; Payá-Vayá, G.; Blume, H. (2013): A Multi-Channel Audio Extension Board for Binaural Hearing Aid SystemsConference ICT.OPEN 2013, Proceedings of ICT.OPEN 2013, (33--37) Weitere Informationen
    ISBN: 978-90-73461-84-0
  • Payá-Vayá, G. (2013): ASIP-Architekturen für digitale Hörgerätesysteme – Ergebnisse aus dem Exzellenzcluster Hearing4allDESIGN&ELEKTRONIK-Entwicklerforum "Electronics goes medical", Tagunsunterlagen DESIGN&ELEKTRONIK-Entwicklerforum "Electronics goes medical"
    ISBN: 978-3-645-50123-1
  • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2013): Development and Potential of Real-Time FPGA Frequency-Based SAR Image Processing for Short-Range FMCW ApplicationsThe 2013 International Conference on Radar (RADAR2013)
  • Kock, M.; Hesselbarth, S.; Blume, H. (2012): Hardware-Accelerated Design Space Exploration Framework for Communication SystemsWireless Innovation Forum Conference on Wireless Communications Technologies and Software Defined Radio (SDR-WInnComm 2012)
  • Nolting, S.; Payá-Vayá, G.; Schmädecke, I.; Blume, H. (2012): Evaluation of a Generic Radix-4 CORDIC Coprocessor Tightly Coupled with a Generic VLIW-SIMD ASIP ArchitectureICT.OPEN 2012 Conference
  • Hartig, J.; Payá-Vayá, G.; Blume, H. (2012): Design and Analysis of a Structured-ASIC Architecture for Implementing Generic VLIW-SIMD ProcessorsICT.OPEN 2012 Conference
    ISBN: 978-90-73461-80-2
  • Giesemann, F.; Payá-Vayá, G.; Blume, H. (2012): A Hardware/Software Environment for Specializing Dynamic Reconfigurable Generic VLIW-SIMD ASIP ArchitectureICT.OPEN 2012 Conference
  • Payá-Vayá, G.; Burg, R.; Blume, H. (2012): Dynamic Data-Path Self-Reconfiguration of a VLIW-SIMD Soft-Processor ArchitectureWorkshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) in conjunction with the 2012 International Conference on Field Programmable Logic and Applications (FPL 2012), (26-29) Weitere Informationen
  • Nowosielski, R.; Zirkelbach, T.; Blume, H. (2012): Evaluation of the RISC-CISC Trade-off for ASIC Implementation in a 250 °C SOI-TechnologyICT.OPEN 2012 Conference
  • Banz, C.; Blume, H.; Pirsch, P. (2012): Evaluation of penalty functions for SGM cost aggregationIntl. Archives of Photogrammetry and Remote Sensing
  • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2012): Close-to-hardware error analysis for real-time wavenumber domain processingRADAR 2012, 7th International Conference on Radar
  • El-Hadidy, M.; El-Absi, M.; Sit, L.; Kock, M.; Zwick, T.; Blume, H.; Kaiser, T. (2012): Improved Interference Alignment Performance for MIMO OFDM Systems by Multimode MIMO AntennasProceedings of the 17th International OFDM Workshop 2012 (InOWo'12)
  • Brückner, H.-P.; Wielage, M.; Blume, H. (2012): Comparison of a Sensor Fusion Algorithm Implementation on a C674X DSP and a CORTEX A8 Core5th European DSP Education and Research Conference, EDERC2012, (15 - 19)
    DOI: 10.1109/EDERC.2012.6532216
    ISBN: 978-1-4673-4595-8
  • Schewior, G.; Blume, H. (2012): Model-based Improvement of Motion Vector Fields for Driver Assistance SystemsConsumer Electronics - Berlin (ICCE-Berlin), 2012 IEEE International Conference on, (231-235)
    DOI: 10.1109/ICCE-Berlin.2012.6336474
    ISBN: 978-1-4673-1546-3
  • Brückner, H.-P.; Blume, H. (2012): Interaktive Bewegungssonifikation zur Unterstützung der Schlaganfall-RehabilitationElectronics goes medical 2012, Design & Elektronik, Weka Fachmedien GmbH
    ISBN: 978-3-645-50105-7
  • Brückner, H.-P.; Wielage, M.; Blume, H. (2012): Intuitive and Interactive Movement Sonification on a Heterogeneous RISC / DSP PlatformProceedings of the 18th International Conference on Auditory Display, Atlanta, GA, USA, 18-21 June 2012. Ed. Michael A. Nees, Bruce N. Walker, Jason Freeman. The International Community for Auditory Display, (75-82) Weitere Informationen
    ISBN: 2168-5126
  • Brückner, H.-P.; Spindeldreier, C.; Blume, H.; Schoonderwaldt, E.; Altenmüller, E. (2012): Evaluation of Inertial Sensor Fusion Algorithms in Grasping Tasks Using Real Input DataWearable and Implantable Body Sensor Networks (BSN), 2012 Ninth International Conference on, (189-194)
    DOI: 10.1109/BSN.2012.9
    ISBN: 978-1-4673-1393-3
  • Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (2012): A flexible hardware architecture for real-time airborne Wavenumber Domain SAR processing9th European Conference on Synthetic Aperture Radar
  • Banz, C.; Dolar, C.; Cholewa, F.; Blume, H. (2011): Instruction Set Extension for High Throughput Disparity Estimation in Stereo Image ProcessingApplication-specific Systems, Architectures and Processors (ASAP), IEEE (169-175)
  • Septinus, K.; Dragone, S.; Langner, M.; Blume, H.; Pirsch, P. (2011): A Scalable Hardware Algorithm for Demanding Timer Management in Network Systems24. PARS - Workshop am 26./27. Mai 2011, Rüschlikon, Switzerland, PARS Mitteilungen GI, ISSN 0177-0454
  • Schmädecke, I.; Blume, H. (2011): GPU-based Acoustic Feature Extraction for Electronic Media ProcessingProceedings of the 14th ITG Conference, Dortmund, Germany
  • Langemeyer, S.; Pirsch, P.; Blume, H. (2011): A FPGA architecture for real-time processing of variable-length FFTs2011 International Conference on Acoustics, Speech and Signal Processing, ICASSP, IEEE (8)
  • Pfitzner, M.; Langemeyer, S.; Pirsch, P.; Blume, H. (2011): A flexible real-time SAR processing platform for high resolution airborne image generationRADAR 2011, 6th International Conference on Radar
  • Nolting, S.; Vaya, P.; Blume, H. (2011): Optimizing VLIW-SIMD Processor Architectures for FPGA ImplementationICT.OPEN 2011 Conference (Veldhoven, Netherlands), USB-Proceedings
  • Banz, C.; Blume, H.; Pirsch, P. (2011): Real-Time Semi-Global Matching Disparity Estimation on the GPUWorkshop on GPU in Computer Vision Applications @ International Conference on Computer Vision (ICCV), IEEE (514-521)
  • Brückner, H.-P.; Bartels, C.; Blume, H. (2011): PC-based real-time sonification of human motion captured by inertial sensorsThe 17th Annual International Conference on Auditory Display, Budapest, Hungary, OPAKFI Egyesület, (8) Weitere Informationen
    ISBN: 978-963-8241-72-6
  • Langemeyer, S.; Pirsch, P.; Blume, H. (2011): Using SDRAMs for two-dimensional accesses of long 2^n x 2^m-point FFTs and transposingConference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS, IEEE
  • Schewior, G.; Flatt, H.; Dolar, C.; Banz, C.; Blume, H. (2011): A Hardware Accelerated Configurable ASIP Architecture for Embedded Real-Time Video-Based Driver Assistance ApplicationsEmbedded Computer Systems (SAMOS), 2011 International Conference on, (209-216)
    DOI: 10.1109/SAMOS.2011.6045463
    ISBN: 978-1-4577-0802-2
  • Payá-Vayá, G.; Martín-Langerwerf, J.; Blume, H.; Pirsch, P. (2010): A Forwarding-sensitive Instruction Scheduling Approach to Reduce Register File Constraints in VLIW ArchitecturesApplication-specific Systems, Architectures and Processors, 2010. ASAP 2010. 21th IEEE International Conference on, François Charot, Frank Hannig, Jürgen Teich, and Christophe Wolinski, IEEE (151-158)
    ISBN: 978-1-4244-6965-9
  • Septinus, K.; Mayer, U.; Pirsch, P.; Blume, H. (2010): A Fully Programmable FSM-based Processing Engine for Gigabytes/s Header Parsing2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IEEE (45-54)
    ISBN: 978-1-4244-7937-5
  • Banz, C.; Hesselbarth, S.; Flatt, H.; Blume, H.; Pirsch, P. (2010): Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-ImplementationInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, (SAMOS X), IEEE (93-101)
    DOI: 10.1109/ICSAMOS.2010.5642077
  • Payá-Vayá, G.; Martín-Langerwerf, J.; Banz, C.; Giesemann, F.; Pirsch, P.; Blume, H. (2010): VLIW Architecture Optimization for an Efficient Computation of Stereoscopic Video ApplicationsThe 2010 International Conference on Green Circuits and Systems, IEEE (457-462)
    ISBN: 978-1-4244-6877-5
  • Mozgova, I.; Brückner, H.-P.; Bach, F.-W.; Blume, H.; Hassel, T.; Kussike, S.-M.; Bierbaum, M.; Brüggeman, P.; Piszczek, M. (2010): Development of a Therapeutic Device Supporting Real-Time Dynamic Vertical Force UnloadInternationales Wissenschaftliches Kolloquium (IWK), Ilmenau, Germany, Univ.-Prof. Dr. rer. nat. habil. Dr. h. c. Prof. h. c. Peter Scharff, Verlag ISLE (468-479) Weitere Informationen
    ISBN: 978-3-938843-53-6
  • Flatt, H.; Blume, H.; Pirsch, P. (2010): Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD ResolutionInternational Conference on Reconfigurable Computing, ReConFig, IEEE (452-457)
    DOI: 10.1109/ReConFig.2010.16
  • Nolte, N.; Moch, S.; Kock, M.; Pirsch, P. (2009): Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreamsAnnual IEEE International SoC Conference, SoCC 2009, Belfast, Northern Ireland, UK, Proceedings, (427-431)
  • Banz, C.; Flatt, H.; Blume, H.; Pirsch, P. (2009): Hardware-Architektur zur echtzeitfähigen Berechnung dichter DisparitätskartenITG Fachtagung für Elektronische Medien "Systeme, Technologien, Anwendungen" 13. Dortmunder Fernsehseminar, VDE
  • Flatt, H.; Blume, S.; Tarnowsky, A.; Blume, H.; Pirsch, P. (2009): Echtzeitfähige Abbildung eines videobasierten Objekterkennungsalgorithmus auf eine modulare Coprozessor-ArchitekturITG Fachtagung für Elektronische Medien "Systeme, Technologien, Anwendungen" 13. Dortmunder Fernsehseminar, VDE
  • Schmädecke, I.; Dürre, J.; Blume, H. (2009): Exploration of Audio Features for Music Genre ClassificationProgram for Research on Integrated Systems and Circuits (ProRISC), Veldhoven, Netherlands, (279-284)
  • Septinus, K.; Nowosielski, R.; Pirsch, P.; Blume, H. (2009): Simulation and Modeling of I/O Protocol Processing with Application of Network Interface Design ExplorationProRISC 2009. 20th Annual Workshop on Circuits, Systems and Signal Processing, (515-521)
  • Payá-Vayá, G.; Martín-Langerwerf, J.; Giesemann, F.; Blume, H.; Pirsch, P. (2009): Instruction Merging to Increase Parallelism in VLIW ArchitecturesInternational Symposium on System-on-Chip 2009, Intl. Symposium on System-on-Chip, J. Nurmi, J. Takala, O. Vainio, IEEE (143-146)
    DOI: 10.1109/SOCC.2009.5335660
    ISBN: 978-1-4244-4465-6
  • Flatt, H.; Schmädecke, I.; Kärgel, M.; Blume, H.; Pirsch, P. (2009): Hardware-Based Synchronization Framework for Heterogeneous RISC/Coprocessor ArchitecturesInternational Symposium on Systems, Architectures, Modeling, and Simulation, SAMOS, IEEE (125-132)
    DOI: 10.1109/ICSAMOS.2009.5289223
  • Blume, H. (2009): Hardware-Plattformen für die Multimedia-Signalverarbeitung –Architekturkonzepte, Entwurfsmethoden, TrendsITG-Fachtagung für elektronische Medien "Systeme, Technologien, Anwendungen", 13. Dortmunder Fernsehseminar
  • Payá-Vayá, G.; Martín-Langerwerf, J.; Moch, S.; Pirsch, P. (2009): An Enhanced DMA Controller in SIMD Processors for Video ApplicationsArchitecture of Computing Systems - ARCS 2009, Lecture Notes in Computer Science(Vol. 5455/2009), Berekovic et al., Springer Berlin / Heidelberg (159-170)
    DOI: 10.1007/978-3-642-00454-4_17
    ISBN: 978-3-642-00453-7
  • Flatt, H.; Blume, S.; Hesselbarth, S.; Schünemann, T.; Pirsch, P. (2008): A Parallel Hardware Architecture for Connected Component Labeling Based on Fast Label MergingInternational Conference on Application-specific Systems, Architectures and Processors, ASAP, IEEE
    DOI: 10.1109/ASAP.2008.4580169
    ISBN: 978-1-4244-1897-8
  • Septinus, K.; Mayer, U.; Starke, W.; Pirsch, P. (2008): Design of a (B)FSM-based Processing EngineCOOL Chips XI, International Symposium on Low-Power and High-Speed Chips, (132)
  • Schleifer, J.; Blume, H.; Noll, G. (2008): Performance Analysis of Networks on Chip Using Coloured Petri NetsProceedings of the ProRISC Workshop
  • Neuenhahn, M.; Schleifer, J.; Blume, H.; Noll, G. (2008): Comparison of Performance Analysis Techniques for Modular and Generic Network-on-ChipTagungsband der URSI Kleinheubacher Tagung 2008
  • Livonius, v.; Blume, H.; Noll, G. (2008): Design of a Pareto-Optimization Environment ant its Application to Motion EstimationProceedings of the International Workshop on Multimedia Signal Processing (MMSP 2008)
  • Sydow, v.; Blume, H.; Kappen, G.; Noll, G. (2008): ASIP-eFPGA architecture for multioperable GNSS receiversProceedings of the SAMOS VIII Workshop (WS-SAMOS), 5114, (136-145)
  • Blume, H.; Haller, M.; Botteck, M.; Theimer, W. (2008): Perceptual Feature based Music Classification A DSP Perspective for a New Type of ApplicationProceedings of the SAMOS VIII Conference (IC-SAMOS), (92-99)
  • Neumann, B.; Sydow, v.; Blume, H.; Noll, G. (2008): Design flow for embedded FPGAs based on a flexible architecture templateProceedings of the DATE 2008
  • Payá-Vayá, G.; Martín-Langerwerf, J.; Taptimthong, P.; Pirsch, P. (2007): Design Space Exploration of Media Processors: A Parameterized SchedulerProceedings of the Intl. Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), IEEE (41-49)
    DOI: 10.1109/ICSAMOS.2007.4285732
    ISBN: 1424410584
  • Payá-Vayá, G.; Jambor, T.; Septinus, K.; Hesselbarth, S.; Flatt, H.; Freisfeld, M.; Pirsch, P. (2007): CHIPDESIGN - From Theory to Real WorldProceedings of the Workshop on Computer Architecture Education in conjunction with the 34th International Symposium on Computer Architecture, ACM (58-64) Weitere Informationen
    ISBN: 978-1-59593-797-1
  • Payá-Vayá, G.; Langerwerf, M.; Pirsch, P. (2007): Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized SchedulerARCS 2007, LNCS 4415, Springer-Verlag, Berlin Heidelberg (254-267)
    DOI: 10.1007/978-3-540-71270-1_19
    ISBN: 3540712674
  • Flügel, S.; Klußmann, H.; Pirsch, P.; Schulz, M.; Cisse, M.; Gehrke, W. (2007): A highly parallel sub-pel accurate motion estimator for H.264IEEE 2006 International Workshop on Multimedia Signal Processing (MMSP-06)
  • Payá-Vayá, G.; Martín-Langerwerf, J.; Pirsch, P. (2007): RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip10th EUROMICRO Conference on Digital System Design (DSD 2007): Architectures, Methods and Tools, IEEE Conference Publishing Services, Los Alamitos (California, USA) (215-221)
    DOI: 10.1109/DSD.2007.4341471
    ISBN: 9780769529783
  • Septinus, K.; Le, T.; Mayer, U.; Pirsch, P. (2007): On the Design of Scalable Massively Parallel CRC CircuitsProceedings of 2007 IEEE International Conference on Electronics, Circuits and Systems, (142-145)
  • Botteck, M.; Blume, H.; Livonius, v.; Neuenhahn, M.; Noll, G. (2007): Programmable Architectures for Realtime Music DecompressionProceedings of the ParaFPGA 2007
  • Zipf, P.; Hinkelmann, H.; Deng, L.; Glesner, M.; Blume, H.; Noll, G. (2007): A Power Estimation Model for an FPGA-based Softcore ProcessorProceedings of the FPL 2007, (171-176)
  • Blume, H.; Livonius, v.; Rotenberg, L.; Bothe, H.; Brakensiek, J.; Noll, G. (2007): Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor PlatformProceedings of the SAMOS VII Conference, (74-81)
  • Sydow, v.; Neumann, B.; Blume, H.; Noll, G. (2007): Design and quantitative analysis of ASIPs with eFPGA-based accelerators as flexible ISA-extensionProceedings of the PhD-Forum DATE 2007 (Design, Automation and Test in Europe)
  • Livonius, v.; Blume, H.; Noll, G. (2007): Flexible Umgebung zur Pareto-Optimierung von Algorithmen - Anwendungen in der VideosignalverarbeitungTagungsband der ITG-Fachtagung Elektronische Medien, 199, (157-162)
  • Nolte, N.; Gehrke, W.; Wiczinowski, F.; Pirsch, P. (2007): SCALABLE MULTI-STANDARD LSI TEXTURE ENCODER FOR MPEG AND VC-1 VIDEO COMPRESSIONMultimedia and Expo, 2007 IEEE International Conference on, (1187-1190)
    DOI: 10.1109/ICME.2007.4284868
    ISBN: 1-4244-1016-9
  • Simon-Klar, C.; Nolte, N.; Langemeyer, S.; Pirsch, P. (2006): Image Data Rate Reduction for an On-Board Real-Time SAR-ProcessorProceedings of EUSAR 2006, VDE-Verlag GmbH, Berlin, Offenbach (CDROM)
    ISBN: 3800729601
  • Sydow, v.; Korb, M.; Neumann, B.; Blume, H.; Noll, G. (2006): Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA MacrosProceedings of the ReConFig'06 Conference, (252-261)
  • Sydow, v.; Neumann, B.; Blume, H.; Noll, G. (2006): Quantitative Analysis of embedded FPGA Architectures for ArithmeticProceedings of the Application Specific Systems, Architectures and Processors Conference 2006 (ASAP 2006), (125-131)
  • Blume, H.; Becker, D.; Botteck, M.; Brakensiek, J.; Noll, G. (2006): Hybrid Functional and Instruction Level Power Modeling for Embedded ProcessorsProceedings of the SAMOS VI Conference, 4017, (216-226)
  • McLaughlin, K.; Kupzog, F.; Blume, H.; Sezer, S.; Noll, G.; McCanny, J. (2006): Design and analysis of matching circuit architectures for a closest match lookupProceedings of the 20th International Parallel and Distributed Processing Symposium 2006 (IPDPS 2006)
  • Kupzog, F.; McLaughlin, K.; Sezer, S.; Blume, H.; Noll, T.; McCanny, J. (2006): Design and Analysis of Matching Circuit Architectures for a Closest Match LookupProceedings of the Advanced International Conference on Telecommunications (IEEE-AICT'06), (224-229)
  • McLaughlin, K.; Sezer, S.; Blume, H.; Yang, X.; Kupzog, F.; Noll, G. (2006): A Scalable Packet Sorting Circuit for High-Speed WFQ Packet SchedulingProceedings of the IEEE SOC Conference 2006, (271-274)
  • Neuenhahn, M.; Blume, H.; Noll, G. (2006): Quantitative analysis of network topologies for NoC-architectures on an FPGA-based emulatorProceedings of the URSI "Advances in Radio Science - Kleinheubacher Berichte''
  • Langemeyer, S.; Simon-Klar, C.; Nolte, N.; Pirsch, P. (2005): Architecture of a Flexible On-Board Real-Time SAR-ProcessorIGARSS 2005, IEEE (CD-ROM)
    ISBN: 0780390512
  • Neumann, B.; Sydow, v.; Blume, H.; Noll, G. (2005): Entwurf und quantitative Analyse parametrisierbarer eFPGA-Architekturen für Arithmetik-AnwendungenProceedings of the URSI Kleinheubacher Tagung 2005
  • Livonius, v.; Blume, H.; Noll, G. (2005): FLPA-based power modeling and power aware code optimization for a Trimedia DSPProceedings of the ProRISC-Workshop
  • Livonius, v.; Blume, H.; Noll, G. (2005): Verwendung von Meta-Bildinformationen zur hochqualitativen BewegungsschätzungTagungsband der ITG-Fachtagung Elektronische Medien (11. Dortmunder Fernsehseminar), (175-180)
  • Blume, H.; Sydow, v.; Becker, D.; Noll, G. (2005): Modeling NoC Architectures by Means of Deterministic and Stochastic Petri NetsProceedings of the SAMOS V Conference, 3553, (374-383)
  • Stolberg, -.; Moch, S.; Friebe, L.; Dehnhardt, A.; Kulaczewski, B.; Berekovic, M.; Pirsch, P. (2004): An SoC with Two Multimedia DSPs and a RISC Core for Video Compression Applications2004 IEEE International Solid-State Circuits Conference Digest of Technical Papers, IEEE, Piscataway, NJ (330-331, 531)
    ISBN: 01936530
  • Simon-Klar, C.; Kirscht, M.; Langemeyer, S.; Nolte, N.; Pirsch, P. (2004): An On-board Real-Time SAR Processor for Small PlatformsProceedings of SPIE Vol. 5574, Remote Sensing for Environmental Monitoring, GIS Applications, and Geology IV, SPIE, Bellingham, WA (420-427)
    ISBN: ISBN 0819455210
  • Neuenhahn, M.; Blume, H.; Noll, G. (2004): Pareto Optimal Design of an FPGA-based Real-Time Watershed Image SegmentationProceedings of the ProRISC Workshop
  • Jachalsky, J.; Wahle, M.; Pirsch, P.; Gehrke, W.; Hinz, T. (2004): A Coprocessor for Intelligent Image and Video Processing in the Automotive and Mobile Communication Domain2004 IEEE International Symposium on Consumer Electronics. Proceedings, IEEE Press, Piscataway, NJ (142-145)
    ISBN: 0780385268
  • Simon-Klar, C.; Kirscht, M.; Langemeyer, S.; Nolte, N.; Pirsch, P. (2004): A Small Real-Time Processor for SAR Image GenerationProceedings EUSAR 2004 5th European Conference on Synthetic Aperture Radar, VDE Verlag GmbH, Berlin (729-732)
    ISBN: 3800728281
  • Blume, H.; Noll, G. (2004): Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri NetsProceedings of the Samos'2004 Workshop, Embedded Systems, Architectures, Modeling and Simulation, 3133, (484-493)
  • Blume, H.; Schneider, M.; Noll, G. (2004): Power Estimation on a Functional Level for Programmable ProcessorsProceedings of the TI Developers Conference 2004
  • Blume, H.; Livonius, v.; Noll, G. (2004): Segmentation in the Loop - An iterative, object based algorithm for motion estimationProceedings of the Visual Communication and Image Processing 2004 (VCIP'04) Conference, (464-473)
  • Patino, M.; Peiro, M.; Ballester, F.; Payá-Vayá, G. (2004): 2D-DCT on FPGA by Polynomial Transformation in Two-DimensionsProceedings of the 2004 International Symposium on Circuits and Systems (ISCAS '04), 3, IEEE (365-368)
    ISBN: 0-7803-8251-X
  • Berekovic, M.; Moch, S.; Pirsch, P. (2003): A Scalable, Clustered SMT Processor for Digital Signal ProcessingMedea Workshop (in conjunction with PACT)
  • Moch, S.; Berekovic, M.; Stolberg, -.; Friebe, L.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core Architecture for Image and Video ApplicationsProceedings MEDEA Workshop at The Twelfth International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), (57-63)
  • Neumann, B.; Feldkämper, H.; Blume, H.; Noll, G. (2003): Application Domain Specific Embedded FPGAsProceedings of the DSP Design Workshop 2003
  • Blume, H.; Kannengiesser, S.; Noll,, G. (2003): Image Quality Enhancement for MRT ImagesProceedings of the ProRISC Workshop
  • Sherstnov, O.; Blume, H.; Noll, G. (2003): Verlustleistungsmodelle für Algorithmen zur Bewegungsschätzung auf FPGAsProceedings der URSI Kleinheubacher Tagung 2003
  • Schneider, M.; Blume, H.; Noll, G. (2003): Verlustleistungsschätzung auf funktionaler Ebene für programmierbare ProzessorenProceedings der URSI Kleinheubacher Tagung 2003
  • Neumann, B.; Blume, H.; Feldkämper, H.; Noll,, G. (2003): Embedded FPGA-Architekturen für Multimedia-ApplikationenProceedings der ITG-Fachtagung "Elektronische Medien", (147-152)
  • Blume, H.; Livonius, v.; Noll, G. (2003): Segmentation in the Loop - Ein iteratives, objektunterstütztes Verfahren zur BewegungsschätzungProceedings der ITG-Fachtagung "Elektronische Medien", (159-164)
  • Payá-Vayá, G.; Peiro, M.; Ballester, F.; Herrero, V.; Colom, R. (2003): New Lifting Folded Pipelined Discrete Wavelet Transform ArchitectureVLSI Circuits and Systems, SPIE International Symposium on Microtechnologies for the New Millennium, 5117, Jose F. Lopez, Juan A. Montiel-Nelson, and Dimitris Pavlidis, SPIE (351-360)
    DOI: 10.1117/12.499049
    ISBN: 0-8194-4977-6
  • Payá-Vayá, G.; Peiro, M.; Ballester, F.; Herrero, V.; Mora, F. (2003): Lifting Folded Pipelined Discrete Wavelet Packet Transform ArchitectureVLSI Circuits and Systems, SPIE International Symposium on Microtechnologies for the New Millennium, 5117, Jose F. Lopez, Juan A. Montiel-Nelson, and Dimitris Pavlidis, SPIE (312-328)
    DOI: 10.1117/12.498992
    ISBN: 0-8194-4977-6
  • Payá-Vayá, G.; Peiro, M.; Ballester, F.; Gadea, R.; Colom, R. (2003): New Distributed Arithmetic Discrete Wavelet Packet Transform ArchitectureVLSI Circuits and Systems, SPIE International Symposium on Microtechnologies for the New Millennium, 5117, Jose F. Lopez, Juan A. Montiel-Nelson, and Dimitris Pavlidis, SPIE (370-378)
    DOI: 10.1117/12.499056
    ISBN: 0-8194-4977-6
  • Stolberg, -.; Berekovic, M.; Friebe, L.; Moch, S.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal ProcessingProceedings 2003 IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Technische Universität Darmstadt, Institute of Microelectronic Systems (155-160)
    ISBN: 3901882170
  • Cerda, J.; Gadea, R.; Payá-Vayá, G. (2003): Implementing a Margolus Neighborhood Cellular Automata on a FPGA7th International Work-Conference on Artificial and Natural Neural Networks (IWANN'03), LNCS - Artificial Neural Nets Problem Solving Methods(2687), Springer Berlin / Heidelberg (121-128)
    DOI: 10.1007/3-540-44869-1_16
    ISBN: 978-3-540-40211-4
  • Payá-Vayá, G.; Peiro, M.; Ballester, J.; Cerda, J. (2003): A New Inverse Discrete Wavelet Packet Transform ArchitectureProceedings of the Seventh International Symposium on Signal Processing and Its Applications (ISSPA'03), II, IEEE (443-446)
    DOI: 10.1109/ISSPA.2003.1224909
    ISBN: 0-7803-7946-2
  • Patino, M.; Peiro, M.; Ballester, F.; Payá-Vayá, G. (2003): Evaluation of 2D-DCT Architecture for FPGAXVIII Conference on Design of Circuits and Integrated Systems (DCIS 2003), IEEE (557-561)
    ISBN: 84-87087-40-X
  • Payá-Vayá, G.; Peiró, M.; Ballester, F.; Mora, F. (2003): Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA13th International Conference on Field Programmable Logic and Application (FPL 2003), LNCS 2778, Springer Berlin / Heidelberg (533-542)
    DOI: 10.1007/978-3-540-45234-8_52
    ISBN: 978-3-540-40822-2
  • Langemeyer, S.; Kloos, H.; Simon-Klar, C.; Friebe, L.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2003): A Compact and Flexible Multi-DSP System for Real-Time SAR ApplicationsProceedings IGARSS2003, IEEE (CD-ROM)
    ISBN: 0780379306
  • Friebe, L.; Stolberg, -.; Berekovic, M.; Moch, S.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A System-on-Chip Architecture with Two Multimedia DSPs and a RISC CoreIEEE International SOC Conference, IEEE, Piscataway, NJ (85-88)
    ISBN: 0780381823
  • Stolberg, -.; Berekovic, M.; Friebe, L.; Moch, S.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal ProcessingProceedings 2003 IEEE Workshop on Signal Processing Systems, IEEE, Piscataway, NJ (189-194)
    ISBN: 0780377958
  • Reuter, C.; Martín, J.; Stolberg, -.; Pirsch, P. (2003): Performance Estimation of Streaming Media Applications for Reconfigurable PlatformsInternational Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS Initiative, Leiden (Die Niederlanden) (42-45)
    ISBN: 9080795712
  • Berekovic, M.; Flügel, S.; Stolberg, -.; Friebe, L.; Moch, S.; Kulaczewski, B.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core Architecture for Image and Video ApplicationsProceedings ICIP2003, IEEE, Piscataway, NJ (101-104)
    ISBN: 0780377508
  • Jachalsky, J.; Wahle, M.; Pirsch, P.; Capperon, S.; Gehrke, W.; Kruijtzer, M.; Nuñez, A. (2003): A Core for Ambient and Mobile Intelligent Imaging ApplicationsProceedings of the 2003 IEEE International Conference on Multimedia & Expo (ICME 2003), IEEE Press, Piscataway, NJ (CDROM)
    ISBN: 0780379667
  • Pirsch, P.; Berekovic, M.; Stolberg, -.; Jachalsky, J. (2003): VLSI Architectures for MPEG-4Proc. 2003 International Symposium on VLSI Technology, Systems, and Applications, IEEE Press, Piscataway, NJ (208-212)
    ISBN: 0780377656
  • Stolberg, -.; Berekovic, M.; Friebe, L.; Moch, S.; Flügel, S.; Mao, X.; Kulaczewski, B.; Klußmann, H.; Pirsch, P. (2003): HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing ApplicationsProceedings Design, Automation and Test in Europe (DATE2003) - Designer's Forum, IEEE, Piscataway, NJ (8-13)
    ISBN: 0769518702
  • Jachalsky, J.; Kulaczewski, B.; Pirsch, P. (2002): Project Management and Verification - The Key Problems of Student Chip Design CoursesProceedings of the 32nd ASEE/IEEE Frontiers in Education Conference (FIE 2002), IEEE Press, Piscataway, NJ (CD-ROM)
    ISBN: 0780374452
  • Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Friebe, L.; Klar, C.; Pirsch, P. (2002): HIPAR-DSP 16, A SCALABLE HIGHLY PARALLEL DSP CORE FOR SYSTEM ON A CHIP VIDEO- AND IMAGE PROCESSING APPLICATIONSAcoustics, Speech, and Signal Processing, 2002 IEEE International Conference on, Volume 3, IEEE, Piscataway (CD-ROM)
    ISBN: 0780374029
  • Blume, H.; Huebert, H.; Feldkämper, H.; Noll, G. (2002): Model based exploration of the design space for heterogeneous Systems on ChipProceedings of the IEEE ASAP Conference, (29-40)
  • Blume, H.; Huebert, H.; Feldkämper, H.; Noll,, G. (2002): Model based exploration of the design space for heterogeneous Systems on ChipProceedings of the IEEE Workshop "Heterogeneous reconfigurable Systems on Chip"
  • Blume, H.; Herczeg, G.; Noll,, G. (2002): Object based refinement of motion vector fields applying probabilistic homogenization rulesDigest of the IEEE Int. Conference on Consumer Electronics, (340-341)
  • Feldkämper, H.; Gemmeke, T.; Blume, H.; Noll,, G. (2002): Analysis of reconfigurable and heterogeneous architectures in the communication domainProceedings of the IEEE ICCSC 2002, (190-193)
  • Blume, H.; Feldkämper, H.; Huebert, H.; Noll, G. (2002): Design Space Exploration for Heterogeneous Systems-on-Chip using cost modelsProc. of the TI developers conference
  • Blume, H.; Peters, G.; Noll, G. (2002): Design Space Exploration of Systems for video signal processing by the example of application oriented picture segmentationProceedings of the IEEE ISCE, (E51-E58)
  • Blume, H. (2002): Model Based Exploration of the Design Space for Heterogeneous Systems-on-CipElektronica Colloquium
  • Sydow, v.; Blume, H.; Noll, G. (2002): Performance-Analyse von General-Purpose und DSP-Kernels für heterogene Systems-on-ChipProceedings of the URSI Kleinheubacher Tagung 2002, (171-175)
  • Feldkämper, H.; Blume, H.; Noll, G. (2002): Analyse von rekonfigurierbaren und heterogenen Architekturen für den Bereich der KommunikationstechnikProceedings of the URSI Kleinheubacher Tagung 2002, (165-169)
  • Payá-Vayá, G.; Mocholi, A.; Sanchez, C.; Ibanez, F. (2002): Sensorial Module of a Module Robot based on Ultrasonic SensorsInternational Conference on Communication, Electronics and Control (TELEC'02), (95)
    ISBN: 84-8138-506-2
  • Payá-Vayá, G.; Martinez-Peiro, M.; Ballester, J.; Gadea, R.; Herrero, V. (2002): Fast Ethernet Media Access Controller CoreDesigners' Forum Proceedings of Design, Automation and Test in Europe (DATE'02), (183-186)
  • Berekovic, M.; Stolberg, -.; Flügel, S.; Moch, S.; Kulaczewski, B.; Friebe, L.; Hilgenstock, J.; Mao, X.; Klussmann, H.; Pirsch, P. (2002): Implementing The MPEG-4 AS Profile on a Multi-Core System on Chip ArchitectureProceedings of 3rd Workshop and Exhibition on MPEG-4 (WEMP4), IEEE, MPEG-4 Industry Forum (M4IF)
  • Jachalsky, J.; Wahle, M.; Pirsch, P.; Gehrke, W. (2002): A Flexible, Fully Configurable Architecture for MPEG-2 Video EncodingProceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), IEEE Press, Piscataway, NJ (1063-1066)
    ISBN: 0780375963
  • Stolberg, -.; Berekovic, M.; Pirsch, P. (2002): A Platform-Independent Methodology for Performance Estimation of Streaming Media ApplicationsProceedings 2002 IEEE International Conference on Multimedia and EXPO (ICME2002), IEEE Press, Piscataway, NJ (CD-ROM)
    ISBN: 0780373057
  • Langerwerf, M.; Reuter, C.; Kropp, H.; Pirsch, P. (2002): Benefits of Macro-based Multi-FPGA Partitioning for Video Processing Applications13th IEEE International Workshop on Rapid System Prototyping, IEEE Computer Society, Los Alamitos CA (60-65)
    DOI: 10.1109/IWRSP.2002.1029739
    ISBN: 076951703X
  • Simon-Klar, C.; Friebe, L.; Kloos, H.; Lieske, H.; Hinrichs, W.; Pirsch, P. (2002): A Multi DSP Board for Real Time SAR Processing using the HiPAR-DSP 16Proceedings of the International Geoscience and Remote Sensing Symposium 2002, IEEE International (2750-2752)
    ISBN: 0780375360
  • Jachalsky, J.; Pirsch, P. (2002): ChipDesign - A Novel Approach to Project-Oriented CoursesProceedings of the 4th European Workshop on Microelectronics Education (EWME 2002), Marcombo de Boixareu Editores, Barcelona (241-243)
    ISBN: 8426713254
  • Kloos, H.; Friebe, L.; Simon-Klar, C.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2002): HiPAR-DSP 16 for the Development of a Scalable Real- Time SAR ProcessorEUSAR 2002, VDE, Berlin (425-428)
    ISBN: 3-8007-2697-1
  • Kulaczewski, B.; Zimmermann, S.; Barke, E.; Pirsch, P. (2001): CHIPDESIGN - A Novel Project-oriented Microelectronics Course2001 International Conference on Microelectronic Systems Education (MSE 2001), IEEE Computer Society, Los Alamitos, USA (71-72)
    ISBN: 0769511562
  • Friebe, L.; Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2001): Multi-DSP-Board for Compact Real-Time Synthetic Aperture Radar SystemsAerosense Conference Proceedings on Technologies for Synthetic Environments: Hardware-in-the-Loop Testing VI, SPIE, Bellingham
    ISBN: 0819440612
  • Stolberg, -.; Berekovic, M.; Pirsch, P.; Runge, H. (2001): Implementing the MPEG-4 Advanced Simple Profile for Streaming Video ApplicationsProceedings International Conference on Multimedia and EXPO (ICME2001), IEEE Press, Piscataway, USA (297-300)
    ISBN: 0769511988
  • Stolberg, -.; Berekovic, M.; Pirsch, P.; Runge, H. (2001): The MPEG-4 Advanced Simple Profile - A Complexity StudyProceedings of the 2nd Workshop and Exhibition on MPEG-4, n/a (33-36)
    ISBN: n/a
  • Kloos, H.; Friebe, L.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (2001): HiPAR-DSP 16, A new DSP for Onboard Real-Time SAR SystemsAerosense Conference Proceedings on Photonic and Quantum Technologies for Aerospace Applications III, SPIE, Bellingham
    ISBN: 0819440817
  • Friebe, L.; Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Klar, C.; Pirsch, P. (2001): A Compact Real-Time SAR Processing System using the Highly Parallel HiPAR-DSP 16International Geoscience and Remote Sensing Symposium 2001, IEEE, Piscataway (CD-ROM)
    ISBN: 0780370333
  • Berekovic, M.; Stolberg, -.; Pirsch, P.; Runge, H. (2001): A Programmable Co-Processor for MPEG-4 VideoInternational Conference on Acoustics, Speech and Signal Processing, IEEE Press, Piscataway, NJ (CD-ROM)
    ISBN: 0780370414
  • Feldkämper, H.; Hübert, H.; Blume, H.; Noll, G. (2001): Analyse rekonfigurierbarer heterogener Systeme anhand einer Komponente für einen UltraschallscannerTagungsband der Kleinheubacher Tagung 2001
  • Blume, H.; Feldkämper, H.; Hübert, H.; Noll,, G. (2001): Analyzing heterogeneous system architectures by means of cost functions: A comparative study for basic operationsProceedings der 27. European Solid State Circuits Conference, (424-427)
  • Blume, H.; Feldkämper, H.; Hübert, H.; Noll,, G. (2001): Operatorbasierte Analyse rekonfigurierbarer heterogener SystemeTagungsband der ITG-Fachtagung Elektronische Medien, (189-194)
  • Blume, H.; Blüthgen, -.; Noll, G. (2001): Integration von hochperformanten ASIC's in rekonfigurierbare Systeme zur Bereitstellung zusätzlicher Multimedia-FunktionalitätenTagungsband des MPC-Workshop
  • Berekovic, M.; Stolberg, -.; Pirsch, P. (2001): Implementing the MPEG-4 AS Profile for Streaming Video on a SOC Multimedia ProcessorProceedings of the 3rd Workshop on Media and Streaming Processors (MSP-3), Keiner (39-44)
    ISBN: Keine
  • Blüthgen, -.; Osterloh, P.; Blume, H.; Noll, G. (2000): A Hardware-Implementation for Approximate Text Search in Multimedia ApplicationsProceedings of the IEEE International Conference on Multimedia and Expo, (1425-1428)
  • Blume, H.; Schwann, R.; Joern, H.; Noll, G. (2000): Ein DSP-basierter echtzeitfähiger Demonstrator zur Power-Doppler-Analyse in medizinischen Ultraschall-SystemenTagungsband der DSP-Deutschland, (191-202)
  • Blume, H.; Blüthgen, -.; Henning, C.; Osterloh,, P. (2000): Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia FunctionalityInternational Conference on Application-specific Systems, Architectures and Processors, (66-75)
  • Blume, H.; Blüthgen, -.; Osterloh, P.; Noll, G. (2000): Coprozessor-Boards zur Integration zusätztlicher Multimedia-FunktionalitätenTagungsband der FKTG-Tagung 2000, (771-788)
  • Berekovic, M.; Pirsch, P.; Selinger, T.; Wels, -.; Miro, C.; Lafage, A.; Heer, C.; Ghigo, G. (2000): Architecture of an Image Rendering Co-Processor for MPEG-4 SystemsProceedings of ASAP 2000, IEEE Computer Society, Los Alamitos, California (15-24)
    ISBN: 0769507166
  • Herrmann, K.; Moch, S.; Hilgenstock, J.; Pirsch, P. (2000): Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated CircuitProceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2000), IEEE Computer Society, Los Alamitos, California (105-113)
    ISBN: 0769507190
  • Wittenburg, P.; Hinrichs, W.; Lieske, H.; Kloos, H.; Friebe, L.; Pirsch, P. (2000): HiPAR-DSP - a Scalable Family of High Performance DSP-CoresProceedings of the 13th Annual IEEE International ASIC/SOC Conference, Institute of Electrical and Electronics Engineers, Inc (IEEE); Piscataway, NJ (92-96)
    ISBN: 0780365984
  • Berekovic, M.; Stolberg, -.; Pirsch, P.; Selinger, T.; Wels, -.; Miro, C.; Lafage, A.; Heer, C.; Ghigo, G. (2000): Co-Processor Architecture for MPEG-4 Main Profile Visual CompositingProceedings International Symposium on Circuits and Systems (ISCAS), IEEE Press, Piscataway, NJ (II 180-183)
    ISBN: 0780354826
  • Stolberg, -.; Berekovic, M.; Pirsch, P.; Runge, H.; Möller, H.; Kneip, J. (2000): The M-PIRE MPEG-4 CODEC DSP and its Macroblock EngineProceedings IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Press, Piscataway, NJ (II 192-195)
    ISBN: 0780354826
  • Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Friebe, L.; Pirsch, P. (2000): HiPAR-DSP 16 A Parallel DSP for Onboard Real-Time Processing of Synthetic Aperture Radar DataInternational Geoscience and Remote Sensing Symposium Proceedings 2000, IEEE, Piscataway, NY, USA (CD-ROM)
  • Hilgenstock, J.; Herrmann, K.; Moch, S.; Pirsch, P. (2000): A Single-Chip Video Signal Processing System with Embedded DRAMIEEE Workshop on Signal Processing Systems 2000 (SIPS), IEEE Press, Piscataway, NJ (23-32)
    ISBN: 0780364880
  • Wittenburg, P.; Meyer, G.; Pirsch, P. (1999): Adapting and Extending Simultaneous Multithreading for High Performance Video Signal Processing ApplicationsWorkshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC)
  • Stolberg, -.; Ohmacht, M.; Pirsch, P. (1999): Cellular Multiprocessor Arrays with Adaptive Resource UtilizationParallel Computation: Proceedings 4th International ACPC Conference, (480-489)
  • Hilgenstock, J.; Herrmann, K.; Pirsch, P. (1999): Memory Organzation of a Single-Chip Video Signal Processing System with Embedded DRAM9th Great Lakes Symposium on VLSI, (42-45)
  • Berekovic, M.; Jacob, K.; Pirsch, P. (1999): Architecture of a Hardware Module for MPEG-4 Shape DecodingProceedings of ISCAS'99, (157-160)
  • Kloos, H.; Wittenburg, P.; Hinrichs, W.; Lieske, H.; Pirsch, P. (1999): A High Performance Digital Signal Processor for Compact Realization of Real-Time Synthetic Aperture Radar SystemsInternational Geoscience and Remote Sensing Symposium Proceedings, (CD-ROM)
  • Kropp, H.; Reuter, C.; Pirsch, P. (1999): An FPGA-based Prototyping System for Video Processing SchemesProceedings 9th International Workshop on Field Programmable Logic and Applications (FPL'99), (333-338)
  • Hinrichs, W.; Wittenburg, P.; Lieske, H.; Kloos, H.; Ohmacht, M.; Pirsch, P. (1999): A 1.3 GOPS Parallel DSP for High Performance Image Processing ApplicationsProceedings of the 25th European Solid-State Circuits Conference (ESSCIRC), (102-105)
  • Kloos, H.; Berekovic, M.; Pirsch, P. (1999): Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-AnwendungenArchitektur von Rechnersystemen (ARCS'99), (5-15)
  • Wittenburg, J.; Hinrichs, W.; Ohmacht, M.; Lieske, H.; Kloos, H.; Pirsch, P. (1999): HiPAR-DSP: Ein 1.3 GOPS Multimedia SignalprozessorArchitektur von Rechensystemen (ARCS '99) GI/ITG Fachtagung, (15-21)
  • Berekovic, M.; Pirsch, P.; Selinger, T.; Wels, -.; Lafage, A.; Miro, C.; Ghigo, G.; Heer, C. (1999): The TANGRAM co-processor for MPEG-4 Visual Compositing1999 IEEE Workshop on Signal Processing Systems (SiPS'99), (311-320)
  • Wittenburg, P.; Pirsch, P.; Meyer, G. (1999): A Multithreaded Architecture Approach to Parallel DSPs for High Performance Image Processing Applications1999 IEEE Workshop on Signal Processing Systems (SiPS '99), (241-250)
  • Pirsch, P. (1999): Architectures for Multimedia Signal ProcessingProceedings 1999 IEEE Workshop on Signal Processing Systems (SiPS'99), (1-12)
  • Berekovic, M.; Lieske, H.; Kloos, H.; Pirsch, P. (1999): Branch Prediction for a SIMD DSP Array ProcessorInternational Conference on Signal Processing Applications and Technology (ICSPAT), (CD-ROM)
  • Hinrichs, W.; Wittenburg, P.; Lieske, H.; Kloos, H.; Ohmacht, M.; Pirsch, P. (1999): A Parallel DSP for High Performance Image Processing ApplicationsInternational Conference on Signal Processing Applications and Technology Proceedings 1999 (ICSPAT), (CD-ROM)
  • Lieske, H.; Wittenburg, J.; Hinrichs, W.; Kloos, H.; Ohmacht, M.; Pirsch, P. (1999): Enhancements for a Second Generation Parallel Multimedia-DSP1st Workshop on Media Processors and DSPs (MP-DSP), (68-77)
  • Berekovic, M.; Stolberg, -.; Pirsch, P.; Möller, H.; Runge, H.; Kneip, J. (1999): The MPIRE MPEG-4 Codec DSP1st Workshop on Media Processors and DSPs (MP-DSP), (62-67)
  • Blüthgen, -.; Blume, H.; Noll, G. (1999): Hardware-Implementierung für die approximative Textsuche in multimedialen AnwendungenITG-Fachtagung Multimedia: Anwendungen, Technologie, Systeme, (229-235)
  • Kropp, H.; Reuter, C.; Wiege, M.; Pirsch, P. (1998): Emulation von Bildverarbeitungsverfahren am Beispiel der Diskreten Cosinus TransformationITG Fachtagung Mikroelektronik für die Informationsverarbeitung, ITG Fachbericht 147 (71-76)
  • Ohmacht, M.; Stolberg, -.; Pirsch, P. (1998): Adaptive Resource Utilization in Cellular Multiprocessor ArraysProceedings 6th IEEE International Workshop on Intelligent Signal Processing and Communication Systems, (571-575)
  • Stolberg, -.; Ohmacht, M.; Pirsch, P. (1998): Dynamic Task Migration in Cellular Multiprocessor ArraysProceedings 2nd IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'98), (206-209)
  • Berekovic, M.; Heistermann, D.; Pirsch, P. (1998): A Core Generator for Fully Synthesizable and Highly Parameterizable RISC-Cores for Systems-On-Chip Designs1998 IEEE Workshop on Signal Processing Systems (SiPS '98), (561-568)
  • Do, T.; Kropp, H.; Reuter, C.; Pirsch, P. (1998): A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAsLecture Notes in Computer Science: Field Programmable Logic and Applications (8th International Workshop FPL'98), 1482, R. W. Hartenstein, A. Keevallik, (441-445)
  • Kropp, H.; Reuter, C.; Pirsch, P. (1998): The Video and Image Processing Emulation System VIPESNinth IEEE International Workshop on Rapid System Prototyping, (170-175)
  • Wittenburg, P.; Hinrichs, W.; Kneip, J.; Ohmacht, M.; Berekovic, M.; Lieske, H.; Kloos, H.; Pirsch, P. (1998): Realization of a Programmable Parallel DSP for High Performance Image Processing ApplicationsDesign Automation Conference (DAC) 1998, (56-61)
  • Hilgenstock, J.; Herrmann, K.; Otterstedt, J.; Niggemeyer, D.; Pirsch, P. (1998): A Video Signal Processor for MIMD MultiprocessingDesign Automation Conference (DAC) 1998, (50-55)
  • Berekovic, M.; Pirsch, P. (1998): An Array Processor with Parallel Data Cache for Image Rendering and CompositingProceedings of Computer Graphics International CGI98, (411-414)
  • Ohmacht, M.; Wittenburg, P.; Pirsch, P. (1998): Influences of Object Based Segmentation onto Multimedia Hardware ArchitecturesInternational Symposium on Circuits and Systems, 4, (45-48)
  • Pirsch, P.; Stolberg, J. (1998): VLSI Architectures for MultimediaInternational Conference on Electronics, Circuits and Systems, 1, (3-11)
  • Berekovic, M.; Pirsch, P. (1998): Architecture of a Coprocessor Module for Image CompositingInternational Conference on Electronics, Circuits and Systems, 2, (203-206)
  • Kropp, H.; Reuter, C.; Do, T.; Pirsch, P. (1998): A Generator for Pipelined Multipliers on FPGAs9th International Conference on Signal Processing Applications and Technology, 1, (669-673)
  • Herrmann, K.; Hilgenstock, J.; Pirsch, P. (1998): A Single Chip Video Coding System with Embedded DRAM Frame Memory for Stand-Alone Applications11th IEEE Int. ASIC Conference 1998, (319-323)
  • Blume, H.; Häring, J.; Schröder, H. (1998): Parallel Evolutionary Optimization of Nonlinear Filters for UpconversionProceedings of the IEEE ProRISC Workshop on Circuits Systems and Signal Processing, (35-42)
  • Franzen, O.; Jostschulte, K.; Blume, H.; Schröder, H. (1998): Einsatz parallelisierter Evolutionsstrategien für den Filterentwurf in der Bildsignalverarbeitung8. Workshop Fuzzy Control des GMA-FA 5.22, (298)
  • Blume, H.; Schmidt, M.; Schröder, H. (1998): Anwendung von Evolutionsstrategien zur Optimierung von Algorithmen der VideosignalverarbeitungVDI/VDE Workshop on Computational Intelligence, (221-236)
  • Freimann, A.; Brune, T.; Pirsch, P. (1998): Mapping of Video Decoder Software on a VLIW DSP MultiprocessorMultimedia Hardware Architectures, Proceedings of SPIE, 3311, (67-78)
  • Berekovic, M.; Meyer, G.; Guo, Y.; Pirsch, P. (1998): A Multimedia RISC Core for Efficient Bitstream Parsing and VLDMultimedia Hardware Architectures, Proceedings of SPIE, 3311, (131-141)
  • Do, T.; Kropp, H.; Reuter, C.; Schwiegershausen, M.; Pirsch, P. (1998): Implementierung von Pipeline-Multiplizierern auf Xilinx FPGAsITG Fachbericht 147, ITG Fachtagung Mikroelektronik für die Informationstechnik 1998, (83-88)
  • Berekovic, M.; Kloos, H.; Pirsch, P. (1998): Parallele Implementierung einer JAVA Virtual Machine mit Erweiterungen für MultimediaITG Fachbericht 147, ITG Fachtagung Mikroelektronik für die Informationstechnik 1998, (305-310)
  • Hinrichs, W.; Wittenburg, P.; Ohmacht, M.; Kneip, J.; Pirsch, P. (1998): HiPAR-DSP: Ein paralleler VLIW RISC-Prozessor für die EchtzeitbildverarbeitungITG Fachbericht 147, ITG Fachtagung Mikroelektronik für die Informationstechnik 1998, (257-262)
  • Berekovic, M.; Frase, R.; Pirsch, P. (1998): A Flexible Processor Architecture for MPEG-4 Image CompositingProceedings of ICASSP'98
  • Do, -.; Kropp, H.; Reuter, C.; Pirsch, P. (1998): Alternative Approaches Implementing High-Performance FIR Filters on Lookup Table-Based FPGAs: A ComparisonProceedings of the SPIE (3526): Configurable Computing: Technology and Applications, SPIE, Bellingham (248-254)
    ISBN: 0819429872
  • Kropp, H.; Schwiegershausen, M.; Do, -.; Reuter, C.; Pirsch, P. (1997): Entwurf von High-Performance-Multiplizierern für Xilinx FPGAs4. SICAN Herbsttagung, Mikroelektronik-Mikrosysteme, (119-122)
  • Ohm, J.; Braun, M.; Rümmler, K.; Blume, H.; Schu, M.; Tuschen, C. (1997): Low Cost-System für universelle Video-FormatkonversionTagungsband der ITG Fach¬tagung Multimedia, (251-256)
  • Blume, H.; Franzen, O.; Schmidt, M. (1997): Optimierung von Algorithmen der Videosignalverarbeitung durch EvolutionsstrategienTagungsband der ITG Fachtagung Multimedia, (215-220)
  • Blume, H.; Franzen, O.; Schmidt, M. (1997): Optimizing Video Signal Processing Algorithms by Evolution StrategiesProceedings of the 5th FUZZY Days, (547-548)
  • Jostschulte, K.; Schwoerer, L.; Blume, H.; Lück, M.; Schröder, H. (1997): Effiziente Simulation heterogener bildverarbeitender SystemeTagungsband des 3. ITG/GI/GMM Workshops Hardwarebeschreibungssprachen und Modellierungsparadigmen, (42-51)
  • Blume, H.; Amer, A.; Schröder, H. (1997): Vectorbased Postprocessing of MPEG Signals for Digital TV ReceiversProceedings of the IS&T/SPIE Symposium on Electronic Imaging
  • Herrmann, K.; Hilgenstock, J.; Pirsch, P. (1997): Architecture of a Multiprocessor System with Embedded DRAM for Large Area IntegrationProceedings of the International Conference on Innovative Systems in Silicon 1997, (274-281)
  • Berekovic, M.; Kloos, H.; Pirsch, P. (1997): Hardware Realization of a JAVA Virtual Machine for High Performance Multimedia Applications1997 IEEE Workshop on Signal Processing Systems (SiPS '97), M. K. Ibrahim, P. Pirsch, J. McCanny, (479-488)
  • Hilgenstock, J.; Herrmann, K.; Wallenberg, v.; Pirsch, P. (1997): Implementation of a Multiprocessor System for Real-Time Video Signal ProcessingProceedings of the International Conference on Electronics, Circuits and Systems (ICECS) 1997, (1423-1426)
  • Wittenburg, P.; Ohmacht, M.; Kneip, J.; Hinrichs, W.; Pirsch, P. (1997): HiPAR-DSP: A Parallel VLIW RISC Processor for Real Time Image Processing ApplicationsProceedings of the International Conference on Algorithms And Architectures for Parallel Processing (ICA3PP) 1997, (155-162)
  • Do, T.; Kropp, H.; Schwiegershausen, M.; Pirsch, P. (1997): Implementation of Pipelined Multipliers on Xlinix FPGAsProceedings of the 7th International Workshop Field-Programmable Logic and Applications (FPL '97), W. Luk, P. Y. K. Cheung, M. Glesner, Springer Verlag (51-60)
  • Reuter, C.; Schwiegershausen, M.; Pirsch, P. (1997): Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary AlgorithmsProceedings of the 1997 International Conference on Application Specific Systems, Architectures, and Processors (ASAP), (294-303)
  • Pirsch, P.; Freimann, A.; Berekovic, M. (1997): Architectural approaches for multimedia processorsIS&T/SPIE Conference: Multimedia Hardware Achitectures, SPIE, 3021, (2-13)
  • Hilgenstock, J.; Herrmann, K.; Pirsch, P. (1997): A Parallel DSP Architecture for Object-based Video Signal ProcessingIS&T/SPIE Conference: Multimedia Hardware Architectures, SPIE, 3021, (78-87)
  • Kneip, J.; Pirsch, P. (1997): Object Oriented Cache Architectures with Parallel Access as On-Chip Memories for Programmable DSPsMikroelektronik'97 - GMM Fachbericht, (149-156)
  • Kneip, J.; Berekovic, M.; Pirsch, P. (1997): An Algorithm-Hardware-System Approach to VLIW Multimedia ProcessorsProceedings of the 1997 IEEE Workshop on Multimedia Signal Processing, Y. Wang, A. R. Reibmann, B. H. Juang, T. Chen, S. Y. Kung, (433-438)
  • Pirsch, P.; Stolberg, J. (1997): Architectural Approaches for Video CompressionProceedings of the 1997 International Conference on Application Specific Systems, Architectures, and Processors (ASAP), (176-185)
  • Blume, H. (1996): Vectorbased Nonlinear Upconversion Applying Center Weighted Medians1996 IS&T/SPIE Symposium on Electronic Imaging, 2662, (142-153)
  • Blume, H.; Appelhans, P.; Bussmann, C.; Schröder, H. (1996): Upconversion MPEG übertragener BildsignaleVortragsband zur FKTG Jahrestagung, (555-572)
  • Blume, H.; Schröder, H. (1996): Image Format Conversion - Algorithms, Architectures, ApplicationsProc. of the IEEE ProRISC Workshop on Circuits, Systems and Signal Processing, (19-37)
  • Schwiegershausen, M.; Kropp, H.; Pirsch, P. (1996): A System Level HW/SW-Partitioning and Optimization ToolEuropean Design Automation Conference (EDAC), (120-125)
  • Herrmann, K.; Hilgenstock, J.; Gaedke, K.; Jeschke, H.; Pirsch, P. (1996): A Programmable Processing Element Dedicated as Building Block for a Large Area Integrated Multiprocessor SystemIEEE International Conference: Innovative Systems in Silicon, (98-103)
  • Herrmann, K.; Gaedke, K.; Hilgenstock, J.; Pirsch, P. (1996): Design of a Development System for Multimedia Applications based on a Single Chip Multiprocessor ArrayICECS, (1151-1154)
  • Herrmann, K.; Gaedke, K.; Jeschke, H.; Pirsch, P. (1996): A Monolithic Low Power Video Signal Processor for Multimedia ApplicationsInternational Conference on Consumers Electronics (ICCE), (176-177)
  • Kneip, J.; Wittenburg, P.; Hinrichs, W.; Berekovic, M.; Pirsch, P. (1996): Der HiPAR-DSP: Ein programmierbarer monolithischer Parallelprozessor für die EchtzeitbildverarbeitungIGT-Fachbericht, VDE-Verlag GmbH (55-60)
  • Kropp, H.; Schwiegershausen, M.; Pirsch, P. (1996): A CAD Tool for the Optimization of Video Signal Processor ArchitecturesProceedings of ICASSP96, IEEE Computer Society Press (1244-1247)
  • Kneip, J.; Pirsch, P. (1996): Memory Efficient List Based Hough Transform for Programmable Digital Signal Processors with On-Chip CachesProc. 1996 IEEE Digital Signal Processing Workshop, (191-194)
  • Kneip, J.; Pirsch, P. (1996): An Object Based Data Cache with Conflict Free Access as Shared Memory of a Parallel DSPProc. 1996 IEEE Intern. Workshop on VLSI Signal Processing IX, (25-34)
  • Winter, M.; Schwiegershausen, M.; Pirsch, P. (1996): Ein CAD-Tool zur Optimierung heterogen aufgebauter Multiprozessoren3. SICAN Herbsttagung, (19-24)
  • Kneip, J.; Ohmacht, M.; Wittenburg, P.; Pirsch, P. (1996): Parallel Implementations of Medium Level Algorithms on a Monolithic ASIMD MultiprocessorProceedings of ISCAS '96, 4, IEEE Press (316-319)
  • Lück, M.; Blume, H. (1995): Konversionstechniken für die zeitsequentielle stereoskopische Bildwiedergabe40. Internationales Wissenschaftliches Kolloqium, Ilmenau, (60-65)
  • Blume, H.; Lück, M. (1995): Bildformatkonversion für Multimedia Displays - Anwendungen, Displayeigenschaften, KonversionsverfahrenBeitrag zur ITG-Fachtagung Multimedia im Rahmen des 6. Dortmunder Fernsehseminars, 136, (49-58)
  • Blume, H.; Amer, A. (1995): Parallel Predictive Motion Estimation using Object Recognition MethodsProceedings of the European Workshop and Exhibition on Image Format Conversion and Transcoding
  • Schröder, H.; Blume, H. (1995): Image Format Conversion - from Signal Theory to ApplicationsProceedings of the European Workshop and Exhibition on Image Format Conversion and Transcoding
  • Pirsch, P.; Gehrke, W. (1995): VLSI Architectures for Video Signal ProcessingIEE Image Processing and its Applications, (6-10)
  • Pirsch, P.; Gehrke, W. (1995): VLSI Architectures for Video CompressionProceedings ISSSE '95, (49-54)
  • Kneip, J.; Wittenburg, P.; Berekovic, M.; Rönner, K.; Pirsch, P. (1995): An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal ProcessorVLSI Signal Processing VIII, (41-51)
  • Pirsch, P.; Kneip, J.; Rönner, K. (1995): Parallelization Resources of Image Processing Algorithms and their Mapping on a Programmable Parallel Videosignal ProcessorIEEE International Symposium on Circuits and Systems, (562-565)
  • Schwiegershausen, M.; Pirsch, P. (1995): A Formal Approach for the Optimization of Heterogeneous Multiprocessors for Complex Image Processing SchemesProceedings of EURO-DAC '95, IEEE Computer Society Press (8-13)
  • Schwiegershausen, M.; Pirsch, P. (1995): A System level Design Methodology for the Optimization of Heterogeneous MultiprocessorsProceedings of 8th International Symposium on System Synthesis, IEEE Computer Society Press (162-167)
  • Pirsch, P.; Gehrke, W. (1995): VLSI Architectures for Video Signal ProcessingVisual Communications and Image Processing 1995, SPIE, 2501, (758-777)
  • Gaedke, K.; Herrmann, K.; Jeschke, H.; Pirsch, P. (1995): AxPe640V - Ein hochintegrierter Videosignalprozessor für die Echtzeit-VideocodierungGME-Fachbericht Mikroelektronik, 15, VDE-Verlag (69-74)
  • Herrmann, K.; Gaedke, K.; Pirsch, P. (1995): Design eines Entwicklungssystems für Multi-Media-Anwendungen auf Basis des programmierbaren Videosignalprozessors AxPe640V6. Dortmunder Fernsehseminar, ITG-Fachbericht, (136), VDE-Verlag (151-156)
  • Winzker, M.; Pirsch, P.; Reimers, J. (1995): Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMsProc. of IEEE Intl. Symposium on Circuits and Systems (ISCAS), (609-612)
  • Blume, H.; Schwoerer, L.; Zygis, K. (1994): Subband Based Upconversion using Complementary Median FiltersProceedings of the 7 th Int. Congress on HDTV and Beyond
  • Blume, H.; Ivanov, K.; Schröder, H. (1994): Proscan - Konversion für Multimedia - Anwendungen - Systemkonzept und VLSI - ArchitekturenTagungsband zur 6. ITG-Fachtagung Mikroelektronik für die Informationstechnik, (109-113)
  • Pirsch, P.; Gehrke, W.; Gaedke, K.; Herrmann, K. (1994): A parallel VLSI Architecture for Object Based Analysis-Synthesis Video CodingIEEE Workshop on Visual Signal Processing and Communications, (136-141)
  • Pirsch, P.; Gehrke, W. (1994): VLSI-Realisierungen für MPEG-VideoMikroelektronik für die Informationstechnik, ITG-Fachbericht 127, VDE-Verlag GmbH (143-152)
  • Gehrke, W.; Hoffer, R.; Pirsch, P. (1994): A Hierarchical Multiprocessor Architecture based on Heterogeneous Processors for Video Coding ApplicationsInternational Conference on Acoustics, Speech and Signal Processing, (II 413-416)
  • Kneip, J.; Rönner, K.; Pirsch, P. (1994): A Single Chip Parallel Architecture for Image Processing ApplicationsSPIE - Visual Communications and Image Processing '94, 2308, (1753-1764)
  • Kneip, J.; Rönner, K.; Pirsch, P. (1994): A Data Path Array with Shared Memory as Core of a High Performance DSPThe International Conference on Application Specific Array Processors, IEEE Computer Society Press (271-282)
  • Pirsch, P.; Gehrke, W.; Gaedke, K.; Herrmann, K. (1994): A Parallel VLSI Architecture for Object-based Analysis-Synthesis CodingIEEE Workshop Visual Signal Processing and Image Communications, (136-141)
  • Herrmann, K.; Seifert, M.; Gaedke, K.; Jeschke, H.; Pirsch, P. (1994): Architecture and VLSI Implementation of a RISC Core for a Monolithic Video Signal ProcessorVLSI Signal Processing VII, J. Rabaey, P. M. Chau, J. Eldon, IEEE (368-377)
  • Schwiegershausen, M.; Pirsch, P. (1994): Optimization of Heterogeneous Multiprocessors for Complex Image Processing ApplicationsProceedings of the IFIP Workshop on Logic and Architecture Synthesis, (251-260)
  • Schwiegershausen, M.; Schönfeld, M.; Pirsch, P. (1994): Abbildung komplexer Bildverarbeitungsverfahren auf heterogene MultiprozessorsystemeRechnergestützter Entwurf und Architektur mikroelektronischer Systeme, Vorträge der 3. GI/ITG/GME-Fachtagung Oberwiesenthal, D. Monjau, (106-115)
  • Blume, H. (1993): Bewegungsschätzung in Videosignalen mit örtlich-zeitlichen PrädiktorenVortragsband zum 5. Dortmunder Fernsehseminar, 0393, (220-231)
  • Winzker, M.; Grüger, K.; Pirsch, P. (1993): Schaltungsstrukturen für die Realisierung integrierter HDTV-TeilbandfilterGME-Fachbericht 11 Mikroelektronik, Vorträge der GME-Fachtagung, Dresden, VDE-Verlag GmbH (345-350)
  • Schönfeld, J.; Pirsch, P. (1993): Single Board Image Processing Unit for Vehicle GuidanceInternational Conference on VLSI, (4.2.1-10)
  • Schönfeld, J.; Pirsch, P. (1993): Image Processing Board for Real-Time Extraction of Line Symbols from Video SequencesVLSI Signal Processing VI, L. D. J. Eggermont, P. Dewilde, E. Deprettere, J. van Meerbergen, IEEE (30-38)
  • Schönfeld, J.; Pirsch, P. (1993): Compact Hardware Realization for Hough Based Extraction of Line Segments in Image Sequences for Vehicle GuidanceICASSP, (I-397-401)
  • Hoffer, R.; Gehrke, W.; Pirsch, P. (1993): Heterogenous multiprocessor architecture for video coding applicationsVideo Communications and PACS for Medical Applications, Proc. of SPIE, 1977, (417-424)
  • Pirsch, P.; Gehrke, W.; Hoffer, R. (1993): A Hierarchical Multiprocessor Architecture for Video Coding ApplicationsInternational Symposium on Circuits and Systems, (1759-1753)
  • Pirsch, P.; Gehrke, W.; Hoffer, R. (1993): Parallel VLSI Implementation of Video Coding AlgorithmsIEEE Workshop on Visual Signal Processing and Communications, (335-338)
  • Gehrke, W.; Hoffer, R.; Pirsch, P. (1993): Hierarchische Multiprozessorarchitekturen für die Echtzeitvideocodierung5. Dortmunder Fernsehseminar, (188-195)
  • Gaedke, K.; Franzen, J.; Pirsch, P. (1993): A Fault-Tolerant DCT-Architecture based on Distributed ArithmeticIEEE International Symposium on Circuits and Systems, (1583-1586)
  • Grüger, K.; Winzker, M.; Gehrke, W.; Pirsch, P. (1992): VLSI Realization of 2D HDTV Subband Filterbanks with On-Chip Line Memories and FIFOsProc. of ESSCIRC '92, 18th European Solid State Circuits Conference, (319-322)
  • Wilberg, J.; Schöbinger, M.; Pirsch, P. (1992): Hierarchical Multiprocessor System for Video Signal ProcessingProc. of SPIE Visual Communications and Image Processing, 1818, (1076-1087)
  • Winzker, M.; Grüger, K.; Pirsch, P. (1992): VLSI Architecture of Filterbanks for an HDTV Subband Coder with 140 Mbit/sForth Int. Workshop on HDTV and beyond, Elsevier (165-172)
  • Winzker, M.; Grüger, K.; Gehrke, W.; Pirsch, P. (1992): Architecture and Realization of HDTV Subband FiltersIEEE workshop on Visual Signal Processing and Communications, Raleigh, NC, S. A. Rajala, K. H. Tzou, IEEE (21-24)
  • Schönfeld, M.; Schwiegershausen, M.; Pirsch, P. (1992): Synthese von Registerschaltungen für den Datentransfer mit systolischen ArraysITG-Fachbericht 122: Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, VDE-Verlag GmbH (147-156)
  • Pirsch, P. (1992): VLSI Architectures and Implementations for Video and HDTVConference on Video/HDTV Signal Processing, University of California, Santa Barbara
  • Pirsch, P. (1992): VLSI Architectures for Digital Video CodingIEEE Workshop on Visual Signal Processing and Communications, S. A. Rajala, K. H. Tzou, IEEE (1-8)
  • Pirsch, P.; Grüger, K.; Winzker, M. (1992): VLSI Architectures of Two-Dimensional Filters for HDTV CodingProc. of IEEE Int. Symposium on Circuits and Systems (ISCAS), 4, IEEE (1648-1651)
  • Jeschke, H.; Gaedke, K.; Pirsch, P. (1992): A VLSI Based Multiprocessor Architecture for Video Signal ProcessingProc. of IEEE Int. Symposium on Circuits and Systems (ISCAS), (1685-1688)
  • Schönfeld, M.; Schwiegershausen, M.; Pirsch, P. (1991): Synthesis of Intermediate Memories needed for the Data Supply to Processor ArraysProc. of VLSI, Halaas, Denyer, (7.3.1-7.3.10)
  • Schönfeld, M.; Pirsch, P.; Schwiegershausen, M. (1991): Synthesis of Intermediate Memories needed to handle the Data Supply to Processor ArraysFifth International ACM & IEEE Workshop on High-Level Synthesis, W. Rosenstiel, (21-28)
  • Rönner, K.; Hecht, V.; Pirsch, P. (1991): Defekttoleranter systolischer Arrayprocessor für die zweidimensionale Faltung von BildsequenzenGME-Fachtagung Mikroelektronik, GME-Fachbericht 8, (95-100)
  • Pirsch, P.; Jeschke, H. (1991): A MIMD multiprocessor system for real-time image processingProc. of the SPIE / SPSE Symposium on Electronic Imaging: Science & Technology, 1452, (544-555)
  • Pirsch, P. (1991): VLSI Architectures and Implementations for Digital Video CodingProc. of Congress: Innovative Developments and Applications of Microelectronics and Information Technologie, E. Raubold, VDE-Verlag GmbH (439-445)
  • Hecht, V.; Rönner, K.; Pirsch, P. (1991): A Defect Tolerant Systolic Array Implementation for Real Time Image ProcessingProc. of Int. Conf. on Application-Specific Array Processors (ASAP), (25-39)
  • Hecht, V.; Rönner, K.; Pirsch, P. (1991): An Advanced Programmable 2D-Convolution Chip for Real Time Image ProcessingProc. of IEEE Intl. Symposium on Circuits and Systems (ISCAS), 4, (1897-1900)
  • Schönfeld, J.; Pirsch, P. (1990): VLSI Implementation for Real Time Processing of Straight Line ExtractionFrom Pixels to Features II, J. C. Simon, Elsevier (395-406)
  • Rönner, K.; Hecht, V.; Pirsch, P. (1990): Defect-Tolerant Implementation of a Systolic Array for Two-Dimensional ConvolutionProc. of IEEE Intl. Conf. on Wafer Scale Integration, IEEE Comp. Soc. Press (19-25)
  • Pirsch, P.; Wehberg, T. (1990): VLSI Architecture of a Programmable Real-Time Video Signal ProcessorProc. SPIE Digital Image Processing and Visual Communications Technologies in the Earth and Athmospheric Sciences, (2-12)
  • Komarek, T.; Pirsch, P. (1990): VLSI Architectures for hierarchical Block Matching AlgorithmsProc. IEEE, Int. Symposium on Circuits and Systems, (45-48)
  • Grüger, K.; Pirsch, P.; Kraus, J.; Reimers, J. (1990): VLSI components for a 560 Mbit/s HDTV codecProc. SPIE Conf. Visual Communications and Image Processing, (388-397)
  • Grüger, K.; Pirsch, P. (1990): VLSI-Komponenten eines 140Mbit/s-HDTV-Codecs14. FKTG-Jahrestagung, (74-75)
  • Pirsch, P.; Schönfeld, J. (1989): VLSI realization of low level image processing unitsProc. of the PROMETHEUS Workshop, (246-253)
  • Münzner, A.; Pirsch, P. (1989): BADGE - Building Block Adviser and GeneratorProc. of IEEE Int. Symp. on Circuits and Systems, 3, (1887-1890)
  • Münzner, A.; Pirsch, P. (1989): BADGE: Ein Programm zur Buildingblock-GenerierungITG-Fachtagung Mikroelektronik für die Informationstechnik, ITG-Fachbericht 110, (35-40)
  • Grüger, K.; Pirsch, P. (1989): Architecture of a 560 Mbit/s DPCM-HDTV-CodecProc. Third Int. Workshop on HDTV, II
  • Komarek, T.; Pirsch, P. (1989): VLSI architectures for block matching algorithmsFirst ESA Workshop on Digital Signal Processing Techniques applied to Space Applications
  • Komarek, T.; Pirsch, P. (1989): VLSI Architectures for Block Matching AlgorithmsProc. IEEE Int. Conf on Acoustics, Speech & Signal Processing (ICASSP), (2457-2460)
  • Komarek, T.; Pirsch, P. (1989): VLSI Architectures for Hierarchical Block Matching AlgorithmsIFIP Workshop on Parallel Architectures on Silicon, (168-181)
  • Pirsch, P.; Komarek, T. (1988): VLSI Architectures for Block Matching AlgorithmsProc. SPIE Conf. Visual Communications and Image Processing III, (882-891)
  • Pirsch, P. (1988): VLSI-Realisierungen für die VideocodierungITG-Fachtagung Mikroelektronik für die Informationstechnik, ITG Fachbericht 103, (119-126)
  • Pirsch, P.; Heiß, R. (1987): Compact video codec for broadband communicationsConference Record TV Symposium Montreux, (206-219)
  • Pirsch, P.; Kemper, A. (1987): HALMA: A program for logic synthesis considering application specific constraintsInternational Workshop on Logic Synthesis
  • Pirsch, P. (1987): Systemarchitektur - Strategien für die schnelle digitale SignalverarbeitungTagungsband der Professorenkonferenz 1987 der DBP, (137-148)
  • Pirsch, P. (1987): VLSI DPCM Codecs for Video Signal CodingPicture Coding Symposium
  • Pirsch, P.; Micke, T.; Bao, H. (1987): Digital Filters for Video Codecs with Oversampled ADC and DACInternational Symposium on Circuits and Systems, (217-220)
  • Pirsch, P. (1986): Architektur und Schaltkreistechnik von CMOS ICs für die Codierung von VideosignalenNTG-Fachbericht Mikroelektronik für die Informationstechnik, (213-222)
  • Pirsch, P. (1985): Coding of TV signals for broadband communicationsConference Record TV Symposium, (599-609)
  • Drews, S.; Pirsch, P.; Schaper, K. (1984): Circuit Technique for VLSI Design of a Video CodecICC'84 Conference Record, (250-255)
  • Pirsch, P. (1983): Codes mit minimaler Wahrscheinlichkeit für PufferspeicherüberlaufNTG-Fachbericht 84, (219-225)
  • Pirsch, P.; Bierling, M. (1983): Changing the Sampling Rate of Video Signals by Rational FactorsConference Record EUSIPCO'83, (171-174)
  • Pirsch, P.; Netravali, N. (1982): Hierarchical Transmission of Multilevel Dithered ImagesInternational Conference on Electronic Image Processing, (16-21)
  • Pirsch, P. (1981): Adaptive Intra-Interframe PrädiktorenSummaries of the 4. Aachener Kolloquium, (163-166)
  • Pirsch, P. (1981): Stability Conditions of DPCM CodersPicture Coding Symposium
  • Pirsch, P. (1981): Adaptive Intra-Interframe DPCM CoderPicture Coding Symposium
  • Pirsch, P. (1980): A New Predictor Design for DPCM Coding of TV SignalsICC'80 Conference Record, (31.2.1-31.2.5)
  • Pirsch, P. (1979): Design of DPCM Quantizers for Video Signals Using Subjective TestsPicture Coding Symposium
  • Pirsch, P. (1979): A New Predictor Design for DPCM CodersPicture Coding Symposium
  • Pirsch, P. (1977): Block Coding of Color Video SignalsNTC Conference Record, (10:5.1-10:5.5)

Journalbeiträge

  • Arndt O. J., Lüders M., Riggers C., Blume H. (2020): Multicore Performance Prediction with MPET - Using Scalability Characteristics for Statistical Cross-Architecture PredictionJournal of Signal Processing Systems, Springer
    DOI: 10.1007/s11265-020-01563-w
  • Giesemann, F.; Gerlach, L.; Payá-Vayá, G.; (2020): Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW CompilersJournal of Signal Processing Systems, (), 1-24
    DOI: 10.1007/s11265-019-01493-2
  • Weißbrich, M.; García-Ortiz, A.; Payá-Vayá, G. (2019): Comparing Vertical and Horizontal SIMD Vector Processor Architectures for Accelerated Image Feature ExtractionJournal of Systems Architecture
    DOI: 10.1016/j.sysarc.2019.101647
  • Weißbrich, M.; Gerlach, L.; Blume, H.; Najafi, A.; García-Ortiz, A.; Payá-Vayá, G. (2019): FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis FrameworkIntegration, the VLSI Journal
    DOI: 10.1016/j.vlsi.2019.01.002
  • Mentzer, N.; Mahr, J.; Payá-Vayá, G.; Blume, H. (2018): Online Stereo Camera Calibration for Automotive Vision based on HW-accelerated A-KAZE-feature ExtractionJournal of Systems Architecture (in press)
    DOI: 10.1016/j.sysarc.2018.11.003
  • Castro Martinez, A.M.; Gerlach, L.; Payá-Vayá, G.; Hermansky, H.; Ooster, J.; Meyer, B.T. (2018): DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parametersSpeech Communication
    DOI: 10.1016/j.specom.2018.11.006
  • Najafi, A.; Weißbrich, M.; Payá Vayá, G.; García-Ortiz, A. (2018): Coherent Design of Hybrid Approximate Adders: Unified Design Framework and MetricsIEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol.8, Issue 4, pp. 736-745
    DOI: 10.1109/JETCAS.2018.2833284
  • Nolting, S.; Payá-Vayá, G.; Giesemann, F.; Blume, H.; Niemann, S.; Müller-Schloer, C. (2017): Dynamic Self-Reconfiguration of a MIPS-Based Soft-Core Processor ArchitectureJournal of Parallel and Distributed Computing Weitere Informationen
    DOI: 10.1016/j.jpdc.2017.09.013
  • Weide-Zaage, K.; Payá-Vayá, G. (2017): COTS – Harsh Condition Effects Considerations from Technology to User LevelAdv. Sci. Technol. Eng. Syst. J. 2(3), 1592-1598 (2017)
    ISBN: ISSN: 2415-6698
  • Payá-Vayá, G.; Bartels, C.; Blume, H. (2017): Small footprint synthesizable temperature sensor for FPGA devicesJournal of Systems Architecture, Volume 76, p. 28–38 Weitere Informationen
    DOI: 10.1016/j.sysarc.2017.03.005
  • Maschhoff, P.; Heene, S.; Lavrentieva, S.; Hentrop, T.; Leibold, C.; Wahalla, M.-N.; Stanislawski, N.; Blume, H.; Scheper, T.; Blume, C. (2017): An intelligent bioreactor system for the cultivation of a bioartificial vascular graftEngineering in Life Sciences Weitere Informationen
    DOI: 10.1002/elsc.201600138
  • Brückner, H.-P.; Lesse, S.; Theimer, W.; Blume, H. (2015): Design space exploration of hardware platforms for interactive low latency movement sonificationJournal on Multimodal User Interfaces
    DOI: 10.1007/s12193-015-0199-y
  • Brückner, H. P.; Lesse, S.; Theimer, W.; Blume, H. (2015): Design space exploration of hardware platforms for interactive low latency movement sonificationJournal on Multimodal User Interfaces, pp. 1-11, Springer Berlin Heidelberg
    DOI: 10.1007/s12193-015-0199-y
  • Mentzer, N.; Payá Vayá, G.; Blume, H. (2015): Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature ExtractionJournal of Signal Processing Systems
    DOI: 10.1007/s11265-015-0986-4
  • Brückner, H.-P.; Krüger, B.; Blume, H. (2014): Reliable orientation estimation for mobile motion capturing in medical rehabilitation sessions based on inertial measurement unitsMicroelectronics Journal 45 (2014), pp. 1603-1611 Weitere Informationen
    DOI: 10.1016/j.mejo.2014.05.018
    ISBN: 0026-2692
  • Kock, M.; Hesselbarth, S.; Pfitzner, M.; Blume, H. (2014): Hardware-Accelerated Design Space Exploration Framework for Communication SystemsAnalog Integrated Circuits and Signal Processing, March 2013, Volume 78, Issue 3, pp 557-571
    DOI: 10.1007/s10470-013-0127-6
  • Brückner, H.-P.; Krüger, B.; Blume, H. (2014): Reliable orientation estimation for mobile motion capturing in medical rehabilitation sessions based on inertial measurement unitsMicroelectronics Journal, Vol. 45, Issue 12, pp. 1603-1611
    DOI: 10.1016/j.mejo.2014.05.018
    ISBN: ISBN: 978-3-319-10947-3
  • Langemeyer, S.; Pirsch, P.; Blume, H. (2012): Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without TransposeInternational Journal of Parallel Programming, Springer (1-24)
    DOI: 10.1007/s10766-012-0225-6
    ISBN: 0885-7458
  • Blume, H.; Bischl, B.; Botteck, M.; Igel, C.; Martin, R.; Roetter, G.; Rudolph, G.; Theimer, W.; Vatolkin, I.; Weihs, C. (2011): Huge Music Archives on Mobile Devices - Toward an automated dynamic organizationIEEE Signal Processing Magazine, Special Issue on Mobile Media Search, 28(4), IEEE, (24-29)
  • Banz, C.; Hesselbarth, S.; Flatt, H.; Blume, H.; Pirsch, P. (2011): Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-ImplementationTransactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), Springer
  • Blume, H.; Flügel, S.; Kunert, M.; Ritter, W.; Sikora, A. (2011): Mehr Sicherheit für FußgängerElektronik automotive, (12.2011), WEKA Fachmedien GmbH (32-37)
    ISBN: 1614-0125
  • Dragon, R.; Dolar, C.; Ostermann, J.; Rieger, M.; Blume, H.; Abel, F.; Kärger, P. (2010): Intelligente VideoüberwachungUnimagazin Leibniz Universität Hannover, 2010(03/04), (34 - 37)
  • Payá-Vayá, G.; Martín-Langerwerf, J.; Pirsch, P. (2010): A Multi-Shared Register File Structure for VLIW ProcessorsJournal of Signal Processing Systems, 58(2), Springer New York (215-231)
    DOI: 10.1007/s11265-009-0355-2
    ISBN: 1939-8018 (Print) 1939-8115 (Online)
  • Flatt, H.; Tarnowsky, A.; Blume, H.; Pirsch, P. (2010): Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-ArchitekturAdvances in Radio Science, 8, (135-142)
    DOI: 10.5194/ars-8-135-2010
  • Blume, H.; Sydow, v.; Rotenberg, L.; Bothe, H.; Brakensiek, J.; Noll, G. (2008): OpenMP-based Parallelization on an MPCore Multiprocessor Platform - A Performance and Power AnalysisJournal of Systems Architecture, 54(11), (1019-1029)
  • Neumann, B.; Sydow, v.; Blume, H.; Noll, G. (2008): Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPsJournal of VLSI Signal Processing, 53(1-2), (129-143)
  • McLaughlin, K.; Sezer, S.; Blume, H.; Yang, X.; Kupzog, F.; Noll, G. (2008): A Scalable Packet Sorting Circuit for High-Speed WFQ Packet SchedulingIEEE Transactions on Very Large Scale Integration, 16(7), (781-791)
  • Blume, H.; Becker, D.; Rotenberg, L.; Botteck, M.; Brakensiek, J.; Noll, G. (2007): Hybrid Functional- and Instruction-Level Power Modeling for Embedded and Heterogeneous Processor ArchitecturesJournal of Systems Architecture, 53(10), (689-702)
  • Blume, H.; Sydow, v.; Becker, D.; Noll,, G. (2007): Application of Deterministic and Stochastic Petri Nets for Performance Modeling of NoC ArchitecturesJournal of Systems Architecture, 53(8), (466-476)
  • Pirsch, P.; Dehnhardt, A.; Flatt, H.; Flügel, S. (2006): Hardware-Realisierungen komplexer Bild- und VideosignalverarbeitungTele Kommunikation Aktuell, 60. Jahrgang, Heft 07-12, Juli-Dezember 2006
  • Pirsch, P. (2006): Seiner Zeit voraus gedachtUni Magazin Hannover, Leibniz, Auf den Spuren des großen Denkers, 3-4, Leibniz Universität Hannover, (36-39)
  • Blume, H.; Sydow, v.; Noll,, G. (2006): A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication DomainJournal of VLSI Signal Processing 2006, 43(2-3), (223-233)
  • Livonius, v.; Blume, H.; Noll, G. (2006): Hochqualitative Bewegungsschätzung unter Verwendung von Meta-BildinformationenEingeladener Beitrag für die Fachzeitschrift Fernseh- und Kinotechnik (FKT), 1-2, (19-24)
  • Stolberg, -.; Berekovic, M.; Moch, S.; Friebe, L.; Kulaczewski, B.; Flügel, S.; Klußmann, H.; Dehnhardt, A.; Pirsch, P. (2005): HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal ProcessingJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 41(1), Springer Science+Business Media (9-20)
    ISBN: 09225773
  • Stolberg, -.; Berekovic, M.; Pirsch, P. (2005): A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing ApplicationsJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 41(2), Springer Science+Business Media B.V., New York (139-151)
    ISBN: 09225773
  • Blume, H.; Feldkämper, H.; Noll, G. (2005): Model-based Exploration of the Design Space for Heterogeneous Systems-on-ChipJournal of VLSI-Signal Processing, 40(1), (19-34)
  • Berekovic, M.; Moch, S.; Pirsch, P. (2004): A scalable, clustered SMT processor for digital signal processingACM SIGARCH Computer Architecture News, 32(3), ACM Press New York, NY, USA (62-69)
    ISBN: 01635964
  • Moch, S.; Berekovic, M.; Stolberg, -.; Friebe, L.; Kulaczewski, B.; Dehnhardt, A.; Pirsch, P. (2004): HiBRID-SoC: A Multi-Core Architecture for Image and Video ApplicationsACM SIGARCH Computer Architecture News, 32(3), ACM Press New York, NY, USA (55-61)
    ISBN: 01635964
  • Blume, H.; Feldkämper, H.; Sydow, v.; Noll, G. (2004): Auf die Mischung kommt es an - Probleme beim Entwurf von zukünftigen Systems-on-Chip (Teil I und II)Elektronik, 19+20, (54-64 und 62-67)
  • Berekovic, M.; Pirsch, P.; Selinger, T.; Miro, C.; Lafage, A.; Wels, -.; Heer, C.; Ghigo, G. (2002): Architecture of an Image Rendering Co-Processor for MPEG-4 Visual CompositingKluwer Journal of VLSI Signal Processing Systems, 31(2), Kluwer Academic Publishers (157-171)
    ISBN: 09225773
  • Blume, H.; Herczeg, G.; Erdler, O.; Noll, G. (2002): Object based refinement of motion vector fields applying probabilistic homogenization rulesIEEE Transactions on Consumer Electronics, 48(3), (694-701)
  • Blume, H.; Bluethgen, -.; Henning, C.; Osterloh, P.; Noll, G. (2002): Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Multimedia FunctionalityJournal of VLSI Signal Processing, 31, (117-126)
  • Berekovic, M.; Stolberg, -.; Pirsch, P. (2002): Multi-Core System-On-Chip Architecture for MPEG-4 Streaming VideoTransactions on Circuits and Systems for Video Technology (CSVT), 12(8), IEEE Periodicals / Transactions/Journals Department (688-699)
    ISBN: 10518215
  • Pirsch, P.; Reuter, C.; Wittenburg, P.; Kulaczewski, B.; Stolberg, -. (2001): Architecture Concepts for Multimedia Signal ProcessingJournal of VLSI Signal Processing Systems, 29(3), Kluwer Academic Publishers, Boston, USA (157-165)
    ISBN: 09225773
  • Reuter, C.; Kropp, H.; Pirsch, P. (2000): Rapid Prototyping von Videosignalverarbeitungsverfahrenit+ti Informationstechnik und Technische Informatik, 42(3), Oldenbourg Verlag (5-9)
    ISBN: 0944-2774
  • Hinrichs, W.; Wittenburg, P.; Lieske, H.; Kloos, H.; Ohmacht, M.; Pirsch, P. (2000): A 1.3 GOPS Parallel DSP for High Performance Image Processing ApplicationsIEEE Journal of Solid-State Circuits, 35(7), IEEE Press, Piscataway, NJ (946-952)
    ISBN: 00189200
  • Berekovic, M.; Kloos, H.; Pirsch, P. (1999): Hardware Realization of a Java Virtual Machine for High Performance Multimedia ApplicationsJournal of VLSI Signal Processing Systems, 22(1), (31-44)
  • Berekovic, M.; Stolberg, J.; Kulaczewski, B.; Pirsch, P.; Möller, H.; Runge, H.; Kneip, J.; Stabernack, B. (1999): Instruction Set Extensions for MPEG-4 VideoJournal of VLSI Signal Processing Systems, 23(1), (27-50)
  • Blume, H. (1999): Nonlinear vector error tolerant interpolation of intermediate video images by weighted mediansSignal Processing: Image Communication, 14(10), (851-868)
  • Berekovic, M.; Pirsch, P.; Kneip, J. (1998): An Algorithm-Hardware-System Approach to VLIW Multimedia ProcessorsJournal of VLSI Signal Processing Systems, 20(1-2), (163-180)
  • Pirsch, P.; Stolberg, -. (1998): VLSI Implementations of Image and Video Multimedia Processing SystemsIEEE Transactions on Circuits and Systems for Video Technology, 8(7), (878-891)
  • Blume, H.; Franzen, O.; Schröder, H. (1998): Algorithmen der Videosignalverarbeitung: Optimierung durch EvolutionsstrategienFKT, 1+2, Hüthig Verlag (43-51)
  • Franzen, O.; Blume, H.; Schröder, H. (1998): FIR-filter design with spatial and frequency design constraints using evolution strategiesEURASIP Signal Processing Journal, 68(3), (295-306)
  • Blume, H. (1997): A new algorithm for nonlinear vectorbased upconversion with center weighted mediansSPIE Journal of Electronic Imaging, 6(3), (368-378)
  • Blume, H. (1997): Nichtlineare fehlertolerante Interpolation von ZwischenbildernDissertation an der Universität Dortmund, 10(503), VDI-Verlag
  • Kneip, J.; Berekovic, M.; Wittenburg, P.; Hinrichs, W.; Pirsch, P. (1997): An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal ProcessorJournal of VLSI Signal Processing, 16(1), (31-40)
  • Pirsch, P.; Stolberg, J.; Chen, K.; Kung, Y. (1997): The Past, Present, and Future of Multimedia Signal ProcessingIEEE Signal Processing Magazine, 14(4), T. Chen, A. Kattsaggelos, S. Y. Kung, (48-51)
  • Kneip, J.; Ohmacht, M.; Rönner, K.; Pirsch, P. (1995): Architecture and C++-Programming Environment of a Highly Parallel Image Signal ProcessorMicroprocessing and Microprogramming, 41(5-6), (391-408)
  • Pirsch, P.; Demassieux, N.; Gehrke, W. (1995): VLSI Architectures for Video Compression - A SurveyProceedings of the IEEE, 83(2), (220-246)
  • Schönfeld, M.; Franzen, J.; Schwiegershausen, M.; Pirsch, P.; Vehlies, U.; Münzner, A. (1995): The LISA Design Environment for the Synthesis of Array Processors Including Memories for the Data Transfer and Fault Tolerance by Reconfiguration and Coding TechniquesJournal of VLSI Signal Processing, 11(1/2), (51-74)
  • Winzker, M.; Pirsch, P. (1994): Reduktion des Schaltfaktors durch das Ausnutzen statistischer Eigenschaften von VideosignalenMikroelektronik, 8(5), (228-291)
  • Hecht, V.; Rönner, K.; Pirsch, P. (1993): A Defect Tolerant Systolic Array Implementation for Real Time Image ProcessingJournal of VLSI Signal Processing, 5(1), (37-47)
  • Musmann, G.; Pirsch, P. (1993): Coding Algorithms and VLSI Implementations for Digital TV and HDTV Satellite BroadcastEuropean Transactions on Telecommunications and Related Technologies, 4(1)
  • Gaedke, K.; Jeschke, H.; Pirsch, P. (1993): A VLSI Based MIMD Architecture of a Multiprocessor System for Real-Time Video Processing ApplicationsJournal of VLSI Signal Processing, 5(2/3), (159-169)
  • Winzker, M.; Grüger, K.; Gehrke, W.; Pirsch, P. (1993): VLSI Chip Set for 2D HDTV Subband Filtering with On-Chip Line MemoriesIEEE Journal of Solid State Circuits, 28(12), (1354-1361)
  • Jeschke, H.; Gaedke, K.; Pirsch, P. (1992): Multiprocessor Performance for Real-Time Processing of Video Coding ApplicationsIEEE Transactions on Circuits and Systems for Video Technology, Special Issue On: VLSI Circuits And Systems for Video Applications, 2(2), (221-230)
  • Pirsch, P.; Speidel, J. (1991): Die Bedeutung der Mikroelektronik für die BildcodierungMikroelektronik, 5(3), VDE-Verlag (110)
  • Grüger, K.; Pirsch, P.; Winzker, M. (1991): VLSI Architectures of Filterbanks for Subband Coding of HDTV SignalsAnnales des Télécommunications, Special Issue VLSI Architectures for Signal Processing, 46(1-2), (110-120)
  • Pirsch, P.; Grüger, K. (1990): Realisierungsaspekte beim zukünftigen hochauflösenden FernsehenMikroelektronik, 4(2), (74-75)
  • Komarek, T.; Pirsch, P. (1989): Array Architektures for Block Matching AlgorithmsIEEE Trans. on Circuits and Systems, 36(10), (1301-1308)
  • Pirsch, P. (1985): Design of a DPCM Codec for VLSI Realization in CMOS TechnologyProceedings of the IEEE, 73(4), (592-598)
  • Musmann, G.; Pirsch, P.; Grallert, J. (1985): Advances in Picture CodingProceedings of the IEEE, 73(4), (523-548)
  • Bostelmann, G.; Pirsch, P. (1985): Coding of Video SignalsElectrical Communications, 59(3), (286-294)
  • Pirsch, P. (1984): Quellencodierung von BildsignalenNTZ, 37/38(1-12/1-3), Arbeitsblattserie
  • Pirsch, P. (1984): Video Codec for Broadband CommunicationsElectrical Communication, 58(4), (447-449)
  • Pirsch, P.; Netravali, N. (1983): Transmission of Gray Level Images by Multilevel Dither TechniquesComputer & Graphics, 7(2), (31-44)
  • Pirsch, P. (1982): Adaptive Intra/Interframe PredictionBell System Techn. Journal, 61(5), (747-764)
  • Pirsch, P. (1982): Stability Conditions of DPCM CodersIEEE Trans. on Communications, COM-30, (1174-1184)
  • Pirsch, P. (1981): Design of DPCM Quantizers for Video Signals Using Subjective TestsIEEE Trans. on Communications, COM-29, (990-1000)
  • Pirsch, P.; Stenger, L. (1976): Statistical Analysis and Coding of Color Video SignalsActa Electronica, 19(4), (277-287)

Dissertationen

  • Payá Vayá, G. (2011): Design and Analysis of a Generic VLIW Processor for Multimedia ApplicationsInformationstechnik, Informationstechnik, Shaker Verlag (194)
    DOI: 10.2370/9783844000641
    ISBN: 978-3-8440-0064-1
  • Blume, H. (1997): Nichtlineare fehlertolerante Interpolation von ZwischenbildernDissertation an der Universität Dortmund, 10(503), VDI-Verlag
    ISBN: 9783183503100

Sonstiges

  • Blume, H.; van de Par, S.; Thiemann, J.; Seifert, C (2020): Sprecherlokalisation in Hörgeräten - Wie Hörgeräte Stimmen im Raum orten könnenUnimagazin : Forschungsmagazin der Leibniz-Universität Hannover, Ausgabe 01|02 2020 Weitere Informationen
    DOI: 10.15488/9967
    ISSN: 1616-4075 - ISSN 0943-5107
  • Blume, H.; Payá-Vayá, G.; Karrenbauer, J.; Benndorf, J.; Blawat, M. (2020): SmartHeaP - Smart Hearing Aid Processor - Ein industrielles Translationsprojekt für digitale HörhilfenUnimagazin : Forschungsmagazin der Leibniz-Universität Hannover, Ausgabe 01|02 2020 Weitere Informationen
    DOI: 10.15488/9973
    ISSN: 1616-4075 - ISSN 0943-5107
  • Blume, H.; Payá-Vayá, G.; Gerlach, L. (2020): KAVUAKA Chip Design für digitale HörhilfenUnimagazin : Forschungsmagazin der Leibniz-Universität Hannover, Ausgabe 01|02 2020 Weitere Informationen
    DOI: 10.15488/9966
    ISSN: 1616-4075 - ISSN 0943-5107
  • Gerlach, L.; Karrenbauer, J.; Payá-Vayá, G.; Blume, H. (2019): High-Performance, Low Power digital hearing aid ASIP/ASICTensilica Day—Trends in Modern Design of Configurable Processors 2019, Hannover, Germany
  • Gerlach, L.; Karrenbauer, J.; Payá-Vayá, G.; Blume, H. (2019): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid SystemWirtschaftsempfang der UVN und der Leibniz Universität Hannover Weitere Informationen
  • Gerlach, L.; Payá-Vayá, G.; Blume, H. (2019): The KAVUAKA Hearing Aid ProcessorEuropractice Activity Report 2018-2019 (http://europractice-ic.com) Weitere Informationen
  • Payá-Vayá, G.; Gerlach, L.; Blume, H. (2018): The KAVUAKA Hearing Aid ProcessorTensilica Day—Trends in Modern Design of Configurable Processors 2018, Hannover, Germany
  • Gerlach, L.; Payá-Vayá, G.; Blume, H. (2018): Analyzing the Trade-Off between Power Consumption and Beamforming Algorithm Performance using a Hearing Aid ASIPTensilica Day—Trends in Modern Design of Configurable Processors 2018, Hannover, Germany
  • Gerlach, L.; Payá-Vayá, G.; Blume, H. (2018): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid SystemTag der Fakultät - Die akademische Jahresfeier Weitere Informationen
  • Gerlach, L.; Seifert, C.; Payá-Vayá, G.; Blume, H. (2018): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid SystemWirtschaftsempfang der UVN und der Leibniz Universität Hannover Weitere Informationen
  • Gerlach, L.; Seifert, C.; Payá-Vayá, G.; Blume, H. (2018): Real-Time Implementation of a GMM-Based Binaural Localization Algorithm on a Low Power Hearing Aid SystemLeibniz-Symposium “Maschinelles Lernen – Intelligente Digitalisierung” Weitere Informationen
  • Behmann, N.; Blume, H. (2018): Low-Power Implementation of CNN-based Object-Detection on Tensilica Vision Series DSPsTensilica Day 2018, Hannover, Germany
  • Payá-Vayá, G.; Roskamp, S.; Webering, F.; Blume, H. (2017): Improving the Processing Performance of a DSP for High Temperature Electronics using Circuit-Level Timing SpeculationTensilica Day—Trends in Modern Design of Configurable Processors
  • Gerlach, L.; Payá-Vayá, G.; Blume, H. (2017): Low-Power Optimization of a VLIW-SIMD ASIP for Hearing Aid DevicesTensilica Day—Trends in Modern Design of Configurable Processors 2017, Hannover, Germany
  • Behmann, N.; Blume, H. (2017): High-Performance, Energy-efficient Computer Vision for ADAS on Tensilica Vision P6Tensilica Day 2017, Hannover, Germany
  • Mentzer, N.; Payá-Vayá, G.; Blume, H. (2016): Analyzing the Performance-Hardware Trade-off of ASIP-based Image Feature ExtractionTensilica Day 2016
  • Gerlach, L.; Seifert, C.; Payá-Vayá, G.; Blume, H. (2016): Instruction-Set Extension based on a 2D Sound Source Localization Algorithm on a Low Power Hearing Aid SystemTensilica Day—Trends in Modern Design of Configurable Processors 2016, Hannover, Germany
  • Gerlach, L.; Nolting, S.; Blume, H.; Payá Vayá, G.; Stolberg, H.; Reuter, C. (2016): A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor ArchitecturesTechnology Transfer in Computing Systems (TETRACOM Technology Transfer Project (TTP), 2016), Prague, Czech Republic
  • Gerlach, L.; Payá Vayá, G.; Blume, H. (2015): FPGA-Based Rapid Prototyping for Exploring and Optimizing Hearing Aid Processors10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), Bremen, Germany
  • Payá Vayá, G.; Gerlach, L.; Nowosielski, R.; Blume, H. (2015): FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), Bremen, Germany
  • Payá-Vayá, G.; Seifert, C.; Blume, H. (2013): Application-Specific Instruction-Set Processors for Ultra-Low-Power Hearing Aid Devices26th International System-on-Chip Conference (SOCC 2013) (invited poster and demo presentation)
  • Brückner, H.-P.; Blume, H. (2012): Mit Hilfe von Tönen wieder schnell mobil werdenTechnik und Leben, Mitgliedermagazin des VDI Bezirksvereins Hannover, 4/2012, VDI, Verein Deutscher Ingenieure
    ISBN: 1433-9897
  • Blume, H.; Brückner, H.-P.; Leibold, C.; Schmädecke, I. (2012): Mikroelektronik-Ausbildung am Institut für Mikroelektronische Systeme der Leibniz Universität HannoverEingeladener Vortrag beim VDI-Workshop “Projektorientiertes und Problem-basiertes Lernen (PBL) in der Ingenieurausbildung“
  • Mentzer, N.; Payá-Vayá, G.; Blume, H. (2012): An ASIP Approach to Find Local Features in Video-Based Surveillance ApplicationsCommunications Signal Processing Workshop 2012 (CSPW 2012)
  • Blume, H. (2008): Modellbasierte Exploration des Entwurfsraumes für heterogene Architekturen zur digitalen VideosignalverarbeitungHabilitation an der RWTH Aachen
  • Jörn, H.; Klein, B.; Schwann, R.; Blume, H.; Noll, G.; Rath, W. (2000): Quantifizierung der Ultraschalluntersuchung im Color-Angio-Verfahren in Echtzeitanalyse - Eine neue MethodeAbstract 17.02.2006 in "Geburtshilfe und Frauenheilkunde"
  • Jörn, H.; Klein, B.; Schwann, R.; Blume, H.; Noll, G.; Rath, W. (2000): Echtzeitanalyse der Plazentadurchblutung im Color-Angio-ModusAbstract 110.6 in "Ultraschall in der Medizin"
  • Amer, A.; Blume, H.; Jostschulte, K.; Lück, M.; Schröder, H. (1997): Verfahren zur Rauschreduktion als Kombination von einer zeitlichen Tiefpaßfilterung und einer kantenerhaltenden örtlichen FilterungPatentanmeldung, P 197 13 177.8
  • Amer, A.; Blume, H.; Jostschulte, K.; Schröder, H. (1995): Verfahren zur Rauschreduktion von Videosignalen mittels BandaufspaltungEuropäische Patentanmeldung, P 19.540.901
  • Blume, H.; Jostschulte, K. (1995): Verfahren und Schaltungsanordnung zur Flimmerreduktion für ein Gerät zur VideosignalverarbeitungEuropäische Patentanmeldung, P 19.505.758.9
  • Blume, H.; Schwoerer, L.; Zygis, K. (1994): Verfahren und Schaltungsanordnung zur Flimmerreduktion für ein Gerät zur VideosignalverarbeitungEuropäische Patentanmeldung, P 4434728.6
  • Blume, H.; Schwoerer, L. (1994): Verfahren zur Umsetzung einer Bildfolge von Halbbildern mit Zeilensprung auf eine Bildfolge von zeilensprungfreien Bildern und Schaltungsanordnung zur Durchführung des VerfahrensEuropäische Patentanmeldung, P 4414173.4

Buchbeiträge

  • Banz, C.; Behmann, N.; Blume, H.; Pirsch, P. (2019): Architectures for Stereo VisionSpringer Handbook on Signal Processing Systems, 3rd Edition, S. Bhattacharyya, E. Deprettere, R. Leupers, J. Takala, Springer
    DOI: 10.1007/978-3-319-91734-4
    ISBN: 978-3-319-91734-4
  • Arndt, O. J.; Rallapalli, P.; Blume, H. (2019): Portable Implementations for Heterogeneous Hardware Platforms in Autonomous Driving Systems (Chapter 6), pages 113-143Big Data Analytics in Cyber-Physical Systems (Elsevier)
    DOI: 10.1016/B978-0-12-816637-6.00006-3
    ISBN: 978-0128166376
  • Badstübner, F.; Ködel, R.; Maurer, W.; Kunert, M.; Rolfsmeier, A.; Perez, J.; Giesemann, F.; Payá Vayá, G.; Blume, H.; Reade, G. (2017): The DESERVE Platform: A Flexible Development Framework to Seemlessly Support the ADAS Development LevelsTowards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems - The DESERVE Approach Weitere Informationen
  • Giesemann, F.; Payá Vayá, G.; Blume, H.; Limmer, M.; Ritter, Werner R. (2017): Deep Learning for Advanced Driver Assistance SystemsTowards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems - The DESERVE Approach Weitere Informationen
  • Mentzer, N.; von Egloffstein, N.; Krüger, L.; Payá Vayá, G.; Blume, H. (2017): Self-Calibration of Wide Baseline Stereo Camera Systems for Automotive ApplicationsTowards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems - The DESERVE Approach Weitere Informationen
  • Meinl, F.; Schubert, E.; Kunert, M.; Blume, H. (2016): Real-time Data Preprocessing for High-Resolution MIMO Radar SensorTowards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems - The DESERVE Approach (in preparation)
  • Weihs, C.; Jannach, D.; Vatolkin, I.; Rudolph, G.: Blume, H. ; et al. (2016): Music Data Analysis: Foundations and ApplicationsChapman and Hall/CRC Weitere Informationen
    ISBN: 9781498719568
  • Brückner, H.-P.; Spindeldreier, C.; Blume, H. (2014): Exploring Energy Efficiency of Hardware-Architectures for IMU based Orientation EstimationSensing Technology: Current Status and Future Trends III, pp 157-178, A. Mason, A.; Mukhopadhyay, S.C.; Jayasundera, K.P.; eds., Springer
    DOI: 10.1007/978-3-319-10948-0_8
    ISBN: 978-3-319-10947-3
  • El-Hadidy, M.; El-Absi, M.; Sit, L.; Kock, M.; Zwick, T.; Blume, H.; Kaiser, T. (2013): Interference Alignment for UWB-MIMO Communication SystemsUltra-Wideband Radio Technologies for Communications, Localization and Sensor Applications
    DOI: 10.5772/55083
    ISBN: 978-953-51-0936-5
  • Banz, C.; Blume, H.; Pirsch, P. (2012): Architectures for Stereo VisionSpringer Handbook on Signal Processing Systems, 2nd Edition (with the editors, scheduled 2012), S. Bhattacharyya, E. Deprettere, R. Leupers, J. Takala, Springer
  • Septinus, K.; Grimm, C.; Rumyantsev, V.; Pirsch, P. (2008): On the Benefit of Caching Traffic Flow Data in the Link BufferEmbedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008, 8th International Workshop, Berekovic, Mladen; Dimopoulos, Nikitas; Wong, Stephan, Springer-Verlag Berlin Heidelberg (2-11)
    ISBN: 978-3-540-70549-9
  • Blume, H.; Sydow, v.; Schleifer, J.; Noll, G. (2008): Petri Net Based Modelling of Communication in Systems on ChipPetri Net - Theory and Applications, I-Tech Education and Publishing
    DOI: 10.5772/5312
    ISBN: 978-3-902613-12-7
  • Flatt, H.; Hesselbarth, S.; Flügel, S.; Pirsch, P. (2007): A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal ProcessingInternational Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS, Lecture Notes in Computer Science, Embedded Computer Systems: Architectures, Modeling, and Simulation(4599/2007), S. Vassiliadis, M. Berekovic, and T.D. Hämäläinen, Springer, Heidelberg (241-250)
    DOI: 10.1007/978-3-540-73625-7
    ISBN: 9783540736257
  • Payá-Vayá, G.; Langerwerf, M.; Pirsch, P. (2005): RAPANUI: Rapid Prototyping for Media Processor Architecture ExplorationSAMOS V Workshop 2005, Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, et al., Springer, Berlin Heidelberg (32-40)
    DOI: 10.1007/11512622_5
    ISBN: 354026969X
  • Reuter, C.; Langerwerf, M.; Stolberg, -.; Pirsch, P. (2004): Performance Estimation of Streaming Media Applications for Reconfigurable PlatformsComputer Systems: Architectures, Modeling, and Simulation, A. Pimentel, S. Vassiliadis, Springer Verlag Berlin Heidelberg (69-77)
    DOI: 10.1007/b98714
    ISBN: 978-3-540-22377-1
  • Pirsch, P.; Freimann, A.; Klar, C.; Wittenburg, P. (2002): Processor Architectures for Multimedia ApplicationsEmbedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, Ed F. Deprettere, Jürgen Teich, and Stamatis Vassiliadis, Springer Verlag, Heidelberg (188-206)
    ISBN: 3540433228
  • Pirsch, P.; Stolberg, -. (1999): Video Signal ProcessingWiley Encyclopedia of Electrical and Electronics Engineering, 23, J. G. Webster, John Wiley & Sons, Inc. (193-205)
  • Pirsch, P.; Gehrke, W. (1998): VLSI Architectures for Image CommunicationsThe Digital Signal Processing Handbook, V. K. Madisetti, D. B. Williams, IEEE Press (59/1-59/21)
  • Pirsch, P.; Berekovic, M.; Freimann, A.; Stolberg, J. (1997): Video Compression ArchitecturesCircuits and Systems in the Information Age, Y. F. Huang, C. H. Wei, IEEE Short Courses at ISCAS 1997 (31-50)
  • Blume, H. (1997): Grundlagen nichtlinearer FilterMehrdimensionale Signalverarbeitung Band 1, Hartmut Schröder, Vieweg+Teubner Verlag (425-471)
    DOI: 10.1007/978-3-663-05679-9
    ISBN: 978-3-663-05680-5
  • Blume, H. (1997): Operatoren zur BildbearbeitungMehrdimensionale Signalverarbeitung Band 1, Hartmut Schröder, Vieweg+Teubner Verlag (379-424)
    DOI: 10.1007/978-3-663-05679-9
    ISBN: 978-3-663-05680-5
  • Schwiegershausen, M.; Schönfeld, M.; Pirsch, P. (1995): Mapping complex Image Processing Algorithms onto Heterogenous Multiprocessors regarding Architecture dependent Performance ParametersAlgorithms and Parallel VLSI Architectures III, M. Moonen, F. Catthoor, Elsevier (353-364)
  • Rönner, K.; Kneip, J.; Pirsch, P. (1995): A Highly Parallel Single-Chip Video Signal ProcessorAlgorithms and Parallel VLSI Architectures III, M. Moonen, F. Catthoor, Elsevier Science B.V. (179-190)
  • Pirsch, P. (1995): VLSI for Video CodingHandbook of Visual Communications, H. M. Hang, J. W. Woods, Academic Press (465-500)
  • Schwiegershausen, M.; Pirsch, P. (1995): Optimization of Heterogeneous Multiprocessors for Complex Image Processing ApplicationsLogic and Architecture Synthesis - State-of-the-art and novel approaches, G. Saucier, A. Mignotte, Chapman & Hall (367-373)
  • Pirsch, P.; Grüger, K. (1994): VLSI Architectures and Circuits for Digital Coding of High Definition TelevisionDesign of VLSI Circuits for Telecommunications and Signal Processing, J. Franca, Y. Tsividis, Prentice Hall (495-527)
  • Pirsch, P.; Wehberg, T. (1994): VLSI Architectures and Circuits for Visual CommunicationsDesign of VLSI Circuits for Telecommunications and Signal Processing, J. E. Franca, Y. Tsividis, Prentice-Hall (429-461)
  • Pirsch, P. (1993): VLSI Implementation StrategiesVLSI Implementations for Image Communications, Series Advances in Image Communications, 2, P. Pirsch, Elsevier (49-68)
  • Grüger, K.; Pirsch, P. (1993): DPCM-CodecsVLSI Implementations for Image Communications, Series Advances in Image Communications, 2, P. Pirsch, Elsevier (311-344)
  • Schönfeld, M.; Schwiegershausen, M.; Pirsch, P. (1992): Synthesis of intermediate memories for the data supply to processor arraysAlgorithms and Parallel VLSI Architectures II, P. Quinton, Y. Robert, Elsevier (365-370)
  • Pirsch, P. (1992): VLSI Architectures for Digital Video Signal ProcessingComputer Systems and Software Engineering, State-of-the-art, P. Dewilde, J. Vandewalle, Kluwer Academic Publ. (65-99)
  • Schönfeld, J.; Pirsch, P. (1991): VLSI Implementation for Real Time Processing of Straight Line ExtractionFrom Pixels to Features II, H. Burkhardt, J. C. Simon, Elsevier (201-211)
  • Grüger, K.; Pirsch, P. (1990): Architecture of a 560 Mbit/s DPCM-HDTV-CodecSignal Proc. of HDTV, II, L. Chiariglione, Elsevier (295-303)
  • Pirsch, P.; Komarek, T. (1989): Systolic Arrays for Block Matching AlgorithmsHigh Precision Navigation, K. Linkwitz, U. Hangleiter, Springer Verlag (354-365)
  • Musmann, G.; Pirsch, P.; Grallert, J. (1989): Advances in Picture CodingVisual Communications Systems, A. N. Netravali, B. Prasada, IEEE Press (67-92)
  • Pirsch, P. (1987): VLSI Design of DPCM Codecs for Video SignalsVisual Communication Systems, A. N. Netravali, B. Prasada, IEEE PRESS (216-227)
  • Pirsch, P. (1980): BildcodierungErfassung und Maschinelle Verarbeitung von Bilddaten, H. Kazmierczak, Springer (85-112)

Bücher

  • Payá-Vayá, G. (Ed.); Blume H. (Ed.) (2017): Towards a Common Software/Hardware Methodology for Future Advanced Driver Assistance Systems Weitere Informationen
    DOI: 10.13052/rp-9788793519138
    ISBN: 9788793519138
  • Barke, E.; Soudris, D.; Pirsch, P. (Ed.) (2000): Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation (PATMOS 2000: Proceedings 10th International Workshop)Springer Verlag, Heidelberg
  • Schröder, H.; Blume, H. (2000): One- and Multidimensional Signal Processing - Algorithms and Applications in Image ProcessingJohn Wiley & Sons Ltd. Weitere Informationen
    ISBN: 978-0-471-80541-0
  • Schröder, H.; Blume, H. (2000): Mehrdimensionale Signalverarbeitung Band 2Vieweg+Teubner Verlag
    ISBN: 978-3519061977
  • Pirsch, P. (1998): Architectures for Digital Signal ProcessingJohn Wiley & Sons, Inc.
  • Ibrahim, K.; Pirsch, P.; McCanny, J. (Ed.) (1997): Signal Processing Systems (SIPS 97)IEEE Press
  • Pirsch, P. (1996): Architekturen der digitalen SignalverarbeitungTeubner
  • Pirsch, P. (1993): VLSI Implementations for Image CommunicationsElsevier Science Publisher
  • Pirsch, P. (1979): Optimierung von Farbfernseh-DPCM-Systemen unter Berücksichtigung der Wahrnehmbarkeit von QuantisierungsfehlernDissertation, University of Hannover