Overlap design for higher tungsten via robustness in AlCu metallizations
- verfasst von
- Jorg Kludt, Kirsten Weide-Zaage, Markus Ackermann, Verena Hein
- Abstract
Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.
- Organisationseinheit(en)
-
Laboratorium f. Informationstechnologie
- Externe Organisation(en)
-
X-FAB Silicon Foundries SE
- Typ
- Aufsatz in Konferenzband
- Seiten
- 137-141
- Anzahl der Seiten
- 5
- Publikationsdatum
- 2013
- Publikationsstatus
- Veröffentlicht
- Peer-reviewed
- Ja
- ASJC Scopus Sachgebiete
- Elektrotechnik und Elektronik, Sicherheit, Risiko, Zuverlässigkeit und Qualität, Elektronische, optische und magnetische Materialien
- Elektronische Version(en)
-
https://doi.org/10.1109/IIRW.2013.6804178 (Zugang:
Unbekannt)
