A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor

verfasst von
Sven Gesper, Daniel Köhler, Gia Bao Thieu, Jasper Homann, Frank Meinl, Holger Blume, Guillermo Payá-Vayá
Abstract

Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8 % lookup tables and +1.8% registers on a Xilinx Ultrascale+ FPGA. A runtime evaluation for two applications from computer vision, namely Deformable Convolutions and point cloud encoding with PointPillars, demonstrates speedups of at least an order of magnitude with the proposed extension.

Organisationseinheit(en)
Institut für Mikroelektronische Systeme
Externe Organisation(en)
Technische Universität Braunschweig
Robert Bosch GmbH
Typ
Aufsatz in Konferenzband
Seiten
167-182
Anzahl der Seiten
16
Publikationsdatum
28.01.2025
Publikationsstatus
Veröffentlicht
Peer-reviewed
Ja
ASJC Scopus Sachgebiete
Theoretische Informatik, Allgemeine Computerwissenschaft
Elektronische Version(en)
https://doi.org/10.1007/978-3-031-78377-7_12 (Zugang: Geschlossen)