Layout optimization of CMOS interconnects for heating, cooling and improved stress distribution

verfasst von

Verena Hein, Kirsten Weide-Zaage, Xi Yang

Abstract

The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors.First simulations which support the development work for optimized interconnect layouts as features to improve the reliability of a circuit were prepared. The evaluations started with the heater development of self-heating test structures for higher metal layers for accelerated reliability tests. It continued with the development of a high robust metal stack. The simulations and the tests at heaters and high robust metallization test structures demonstrated the advantages of such a layout improvement.The simulations of the distribution of the temperature and the mechanical stress illustrates the important parameters and their interactions.The paper presents new ANSYS® -simulations on some exemplary heater layout variants in the highly robust metallization design. The scientific questions were the suitability and the benefits of such a heater layout for heating, cooling and stress distribution in CMOS circuits. Different heater-test line models have been analysed by ANSYS® -simulations. The variants of the models were forced or no forced current in heater and/or test line and the kind of metal layer of heater connection. The current density, temperature, their gradients, the hydrostatic stress, the Von Mises stress and the mass flux divergences have been analysed.Such simulations can be utilized to improve parts of circuits like chip corners, sensitive transistors, circuits on GaN-substrate, with TSVs or applications with 3D integration. The local temperature and stress management can be improved by the special metallization layout and the improvement can be supported by simulation data.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Externe Organisation(en)

X-FAB Silicon Foundries SE

Typ

Aufsatz in Konferenzband

Publikationsdatum

03.2019

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektronische, optische und magnetische Materialien, Fließ- und Transferprozesse von Flüssigkeiten, Elektrotechnik und Elektronik, Maschinenbau, Sicherheit, Risiko, Zuverlässigkeit und Qualität, Modellierung und Simulation

Elektronische Version(en)

https://doi.org/10.1109/eurosime.2019.8724562 (Zugang: Geschlossen)