Degradation behavior in upstream/downstream via test structures

verfasst von

J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein, C. Kovács

Abstract

The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. The lifetime of up- and downstream test structures with different overlaps as well as strong misalignment was determined by measurements. Investigations have shown that the alignments have a noticeable effect on the reliability and performance of test structures. The downstream line shows the expected lifetime behavior. For the upstream line no influence of the misalignment on the lifetime was found. Simulations are taken into account to understand the thermal-electrical and mechanical behavior.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Externe Organisation(en)

X-FAB Silicon Foundries SE

Typ

Artikel

Journal

Microelectronics reliability

Band

54

Seiten

1724-1728

Anzahl der Seiten

5

ISSN

0026-2714

Publikationsdatum

01.09.2014

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektronische, optische und magnetische Materialien, Atom- und Molekularphysik sowie Optik, Sicherheit, Risiko, Zuverlässigkeit und Qualität, Physik der kondensierten Materie, Oberflächen, Beschichtungen und Folien, Elektrotechnik und Elektronik

Elektronische Version(en)

https://doi.org/10.1016/j.microrel.2014.07.042 (Zugang: Geschlossen)