Three-dimensional voids simulation in chip metallization structures

A contribution to reliability evaluation

verfasst von

D. Dalleau, K. Weide-Zaage

Abstract

The understanding of metal migration mechanisms remains today a big interest. Metallization structures are getting more and more smaller whereas the reliability of integrated circuits needs to be improved. The increasing capacities of numerical analysis and simulation tools like the Finite Element Method (FEM) allow the prediction of failure location degradation caused by this phenomena. In this paper, an algorithm for 3-D simulation of void formation in metallizations is presented, taking into account the electromigration, as well as the thermomigration and the stressmigration contributions. Two typical structures like a meander- and a pad structure are investigated. The void evolution inside the metallization structure, as well as the change of the electrical resistivity of the interconnect are simulated. A new method for the time-dependent calculation of the phenomena is also proposed, and an evaluation of the Time-To-Failure (TTF) for the investigated structures is presented. The results obtained by simulation are found in good agreement with SEM observations.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Artikel

Journal

Microelectronics reliability

Band

41

Seiten

1625-1630

Anzahl der Seiten

6

ISSN

0026-2714

Publikationsdatum

09.2001

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektronische, optische und magnetische Materialien, Atom- und Molekularphysik sowie Optik, Sicherheit, Risiko, Zuverlässigkeit und Qualität, Physik der kondensierten Materie, Oberflächen, Beschichtungen und Folien, Elektrotechnik und Elektronik

Elektronische Version(en)

https://doi.org/10.1016/S0026-2714(01)00151-2 (Zugang: Unbekannt)