RAPANUI

Rapid prototyping for media processor architecture exploration

verfasst von

Guillermo Payá Vayá, Javier Martín Langerwerf, Peter Pirsch

Abstract

This paper describes a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The new methodology combines a typical ASIC flow with an FPGA flow focused on rapid prototyping. In order to make an exhaustive verification of the system architecture, a reference model that specifies the hardware implementation is used for validating both, HDL description and emulated system. Functional coverage in addition to traditional code coverage is used to test 100% of data, control and structural hazards of the system architecture. The reference model is also part of a stand-alone simulation environment. This allows hardware and application development be supported by a unique system model.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Typ

Konferenzaufsatz in Fachzeitschrift

Journal

Lecture Notes in Computer Science

Band

3553

Seiten

32-40

Anzahl der Seiten

9

ISSN

0302-9743

Publikationsdatum

2005

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Theoretische Informatik, Informatik (insg.)

Elektronische Version(en)

https://doi.org/10.1007/11512622_5 (Zugang: Geschlossen)