A modular coprocessor architecture for embedded real-time image and video signal processing

verfasst von

Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch

Abstract

This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Typ

Aufsatz in Konferenzband

Seiten

241-250

Anzahl der Seiten

10

Publikationsdatum

2007

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Theoretische Informatik, Informatik (insg.)

Elektronische Version(en)

https://doi.org/10.1007/978-3-540-73625-7_26 (Zugang: Offen)