Hardware Implementation and Evaluation of a Feature Extractor for Camera-based Driver Assistance Systems

High reliability and robustness of modern driver assistance systems under arbitrary traffic, weather and illumination conditions often is a problem. In the future, there is a need for more complex algorithms to provide even more reliable information as a basis to make autonomous decisions in the car. Cost-efficient stereo camera systems with high resolution are capable of providing sufficient image data, which can be used for various applications. However, often there is a lack of computational power in the subsequent image processing hardware to evaluate the data with robust state-of-the-art methods at high framerate for a short response-time of the system, at high resolution and at low power consumption.

To address the above mentioned challenges, research is done by the “Architectures and Systems” group of the Institute of Microelectronic Systems towards the development of new concepts within the application field of advanced driver assistance systems (ADAS) and image processing. Thereby, special interest lies in the implementation of efficient FPGA architectures, as they can provide high performance processing while at the same time offering a good flexibility by reconfiguration.

One of the key components in image processing for driver assistance systems is the extraction of distinctive features such as corners and their description based on the surrounding pixels. Good features should offer a high repeatability over an image sequence, which allows matching them from one frame to another. This provides the basis for a variety of different algorithms such as optical flow, camera calibration, egomotion estimation and object recognition. Therefore, feature extraction is frequently used as preliminary operation on the pixel-level demanding high performance processing.

In this thesis, Florian Kluger gets the task to implement the “FAST” feature extractor and the “BRIEF” feature descriptor in software, as verification reference, and in hardware for an exemplary FPGA. Both implementations shall be evaluated for different algorithmic parameters and architectural trade-offs towards their performance influence when processing image sequences of typical car driving scenes. An efficient utilization of the FPGA resources needs to be ensured. Finally, the functionality of the hardware architecture shall be evaluated in emulation.