RAPANUI

A case study in rapid prototyping for multiprocessor system-on-chip

authored by

Guillermo Payá-Vayá, Javier Martín-Langerwerf, Peter Pirsch

Abstract

This paper describes a case study in a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The goal of the presented methodology is to speed up and improve the verification flow of a multiprocessor system that will finally be implemented as an ASIC. The case study consists of a 64-bit compatible AMBA AHB system bus which connects up to 14 32-Bit RISC processors to a host interface. A typical parallel computing application has been implemented for the parameterized multiprocessor system. The employed FPGA emulation environment increases by up to 200 the simulation frequency of the global system on a workstation (2.2 GHz AMD Dual Opteron with 8 GB RAM). Moreover a stand-alone emulation can be performed at the maximum achievable frequency (65 MHz).

Organisation(s)

Institute of Microelectronic Systems

Type

Conference contribution

Pages

215-221

No. of pages

7

Publication date

2007

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Hardware and Architecture, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1109/DSD.2007.4341471 (Access: Closed)