High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments

authored by: Malte Hawich, Nico Rumpeltin, Malte Rücker, Tobias Stuckenberg, Holger Blume
Abstract: An increasing number of sensors and actuators are being
used in today’s high-tech drilling tools to further optimise the drilling
process. Each sensor and actuator either generates data that needs to
be processed or requires real-time input control signals. RISC-V proces-
sors are being developed to meet the computational demands of today’s
harsh environment applications. A known bottleneck for processors is
the data flow and instruction input to the processor, especially as mem-
ory response times are particularly high for the state-of-the-art 180 nm
harsh environment silicon-on-insulator (SOI) technology, further limit-
ing the design space. Therefore, this paper presents a high-performance
instruction fetch architecture that achieves a high clock frequency while
preserving high instructions per cycle. We evaluate different approaches
to implementing such a design and propose a design that is able to reach
up to 0.73 instructions per cycle (IPC) and achieve a clock frequency of
229 MHz, which is more than twice as high as previous designs in this
technology. The new architecture achieves 167 million instructions per
second (MIPS), which is four times higher than the rocket chip achieves
when synthesised for the same harsh environment technology.
Organisation(s): Architectures and Systems Section
Type: Contribution to book/anthology
Volume: 23
Pages: 255-268
No. of pages: 14
Publication date: 2023
Publication status: Published
Peer reviewed: Yes
ASJC Scopus subject areas: Theoretical Computer Science, Computer Science(all)
Research Area (based on ÖFOS 2012): Computer architecture
Electronic version(s): https://doi.org/10.1007/978-3-031-46077-7_17 (Access: Closed)