A multi-shared register file structure for VLIW processors

authored by: Guillermo Payá-Vayá, Javier Martín-Langerwerf, Peter Pirsch
Abstract: The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.
Organisation(s): Institute of Microelectronic Systems
Type: Article
Journal: Journal of Signal Processing Systems
Volume: 58
Pages: 215-231
No. of pages: 17
ISSN: 1939-8018
Publication date: 20.03.2009
Publication status: Published
Peer reviewed: Yes
ASJC Scopus subject areas: Control and Systems Engineering, Theoretical Computer Science, Signal Processing, Information Systems, Modelling and Simulation, Hardware and Architecture
Electronic version(s): https://doi.org/10.1007/s11265-009-0355-2 (Access: Closed)