Processor Architecture Tradeoffs for On-Site Electronics in Harsh Environment

Microcontroller units placed in harsh environments are manufactured using large semiconductor technology nodes in order to provide reliable operation even at high temperatures or increased radiation exposition. As a drawback, these large technology nodes provide rather high gate propagation delays drastically reducing the system performance. Additionally, when reducing area costs and power consumption, the actual processor architecture becomes a major design point. A processor architecture is defined by several parameters like data path width, type of instruction execution, or the actual underlying architectural design paradigm. This work presents a design space exploration of four different architecture paradigms implemented for a 0.35μm high temperature SOI CMOS technology.