Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization

authored by

Jan-Luca Frühauf, Malte Hawich, Holger Christoph Blume

Abstract

Processor performance is often limited by cache efficiency, a critical aspect in any signal processing task. A RISC-V processor combined with the cache presented in this paper will be part of a deep drilling component manufactured to further automate the entire drilling process. Therefore, signal acquisition, storage, and in-situ processing are required. This paper presents a data cache optimization for a high performance RISC-V processor designed to operate under extreme conditions up to 175°C and 200MPa while maintaining a stable frequency of 180MHz. At the heart of this new design is XFAB’s XT018 technology, a state-of-the-art 180nm SOI technology capable of withstanding the harsh environment in which the core will operate. Memories matching the required clock frequencies will only provide single-port access, adding further challenges to the design. Several caching strategies and implementations are applied and compared to each other in this paper. The design is implemented with a direct connection to the RISC-V core on the one side and a connection to an AXI4 network on the other side. We build this cache that supports multi-port access, with only a single-port SRAM memory at its core. Despite the inherent limitations of single-port SRAMs and the harsh environmental conditions, our design successfully implements a cache system that achieves an impressive hit rate of more than 97%, which is in line with industry standards for consumer grade electronics typically operating at room temperature.

Organisation(s)

Architectures and Systems Section

Type

Conference contribution

Pages

1-4

No. of pages

4

Publication date

2024

Publication status

Published

Peer reviewed

Yes

Electronic version(s)

https://doi.org/10.1109/PACET60398.2024.10497077 (Access: Closed)