Programmable processing element dedicated as building block for a large area integrated multiprocessor system

authored by

Klaus Herrmann, Joerg Hilgenstock, Klaus Gaedke, Hartwig Jeschke, Peter Pirsch

Abstract

The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. It consists of a RISC processor supplemented by a low level coprocessor for computation intensive convolution-like tasks. Several of the processing elements can be bus-connected to built a coarse-grained MIMD based large area integrated multiprocessor system. Each of the processor elements provides high performance for video coding tasks in order to keep the overall number of required processing elements for complex real-time video coding applications small. A key feature of the processing element to support large area integration is a unidirectional data supply which allows reconfiguration strategies for the interconnection network. Furthermore on-chip program and data memories have been implemented in order to relax the overall bandwidth requirements of the large area integrated multiprocessor system.

Organisation(s)

Architectures and Systems Section

Type

Conference contribution

Pages

98-103

No. of pages

6

Publication date

1996

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Condensed Matter Physics, Electrical and Electronic Engineering, Hardware and Architecture

Electronic version(s)

https://doi.org/10.1109/ICISS.1996.552416 (Access: Closed)