A multi-core SoC design for advanced image and video compression
- authored by
- A. Dehnhardt, M. B. Kulaczewski, L. Friebe, S. Moch, P. Pirsch, H. J. Stolberg, C. Reuter
- Abstract
A flexible SoC architecture and its hardware implementation targeting advanced MPEG-4 video coding and region-of-interest detection (ROI) is presented. The multi-core architecture integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to different computational characteristics, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, and operates at 145 MHz. A surveillance application example includes a MPEG-4 Simple Profile encoder with preceding ROI detection for superior compression results in full TV resolution.
- Organisation(s)
-
Institute of Microelectronic Systems
- External Organisation(s)
-
videantis GmbH
- Type
- Conference contribution
- Pages
- V665-V668
- Publication date
- 2005
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- Software, Signal Processing, Electrical and Electronic Engineering
- Electronic version(s)
-
https://doi.org/10.1109/ICASSP.2005.1416391 (Access:
Closed)
