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A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework

authored by

Moritz Weißbrich, Guillermo Payá-Vayá, Lukas Gerlach, Holger Blume, A. Najafi, A. García-Ortiz

Abstract

ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. For an exemplary timing analysis campaign of an existing chip design, speed-up factors of up to 267 are achieved while maintaining timing behavior deviations lower than 1.05% to timing simulations.

Organisation(s)

Institute of Microelectronic Systems

External Organisation(s)

University of Bremen

Type

Conference contribution

Pages

1-8

No. of pages

8

Publication date

09.2017

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Modelling and Simulation, Computer Networks and Communications, Hardware and Architecture, Energy Engineering and Power Technology, Electrical and Electronic Engineering, Control and Optimization

Sustainable Development Goals

SDG 7 - Affordable and Clean Energy

Electronic version(s)

https://doi.org/10.1109/PATMOS.2017.8106956 (Access: Closed)