Design space exploration of media processors

A parameterized scheduler

authored by: Guillermo Payá-Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch
Abstract: This paper describes an enhanced list scheduling algorithm used on a parameterized assembler. The assembler, which is configurable in terms of architectural parameters, is used on a new environment system for exploring and optimizing VLIW architectures for multimedia applications. A generic VLIW architecture with a novel register file structure is used as a base architecture. The proposed scheduling algorithm includes sophisticated features. A backtracking technique allows to undo inappropriate scheduling decisions, while an advanced resource conflict function allows to work with different VLIW architecture configurations. Moreover, local register allocation in conjunction with the instruction scheduling process is also implemented for obtaining better code compaction. Two different multimedia tasks are implemented to check the correctness of the generated code for different architecture configurations. The code compaction efficiency, when scheduling these applications for different VLIW architecture configurations with a partitioned register file and limited number of functional units, reaches up to 94% of the compaction efficiency for the same configuration with an unconstrained register file and unlimited number of functional units.
Organisation(s): Institute of Microelectronic Systems
Type: Conference contribution
Pages: 41-49
No. of pages: 9
Publication date: 2007
Publication status: Published
Peer reviewed: Yes
ASJC Scopus subject areas: Computer Science(all), Hardware and Architecture, Control and Systems Engineering
Electronic version(s): https://doi.org/10.1109/ICSAMOS.2007.4285732 (Access: Closed)