A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs

authored by

Jesko Flemming, Bernhard Wicht, Pascal Witte

Abstract

This paper presents a new architecture as well as a compensation method for discrete-time (DT) noise-canceling SMASH (NC-SMASH) bandpass delta-sigma modula-tors (BP-ΔΣMs). The proposed method relaxes timing constraints on the feedback path by one clock cycle, which in turn relaxes the timing constraints on the adder in front of the quantizer, and the digital adder for the SMASH architecture. In SMASH architectures, this relaxed timing enables an NC analog-to-digital converter (ADC) architecture. Unlike state-of-the-art solutions, which require an analog unit delay at the ADC's input to achieve these relaxed requirements, the presented bandpass approach renders this analog delay and the respective input capacitor unnecessary. In a respective circuit implementation this significantly reduces the area and power consumption. The proposed compensation method allows the designer to choose between a non-delayed input and an elimination of the input signal component inside the loop filter, which would require a delayed input path.

Organisation(s)

Institute of Microelectronic Systems
Laboratory of Nano and Quantum Engineering

External Organisation(s)

University of Applied Sciences and Arts Hannover (HsH)

Type

Conference contribution

Publication date

2023

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1109/ISCAS46773.2023.10181385 (Access: Closed)