Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures

authored by

H. Blume, T. von Sydow, D. Becker, T. G. Noll

Abstract

The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects. In this contribution the modeling of basic NoC communication scenarios featuring different processor cores, network topologies and communication schemes is presented. In order to provide a testbed for the verification of modeling results a state-of-the-art FPGA-platform has been utilized. This platform allows to instantiate a soft-core processor network which can be adapted in terms of communication network topologies and communication schemes. It will be shown that DSPN modeling yields good communication performance prediction results at low modeling effort. Different DSPN modeling aspects in terms of accuracy and computational effort are discussed.

External Organisation(s)

RWTH Aachen University

Type

Article

Journal

Journal of Systems Architecture

Volume

53

Pages

466-476

No. of pages

11

ISSN

1383-7621

Publication date

21.12.2006

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Software, Hardware and Architecture

Electronic version(s)

https://doi.org/10.1016/j.sysarc.2006.11.001 (Access: Closed)