HIBRID-SOC
A multi-core architecture for image and video applications
- authored by
- S. Moch, M. Bereković, H. J. Stolberg, L. Friebe, M. B. Kulaczewski, A. Dehnhardt, P. Pirsch
- Abstract
The HiBRID-SoC multi-core architecture targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video de-encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces on a single chip, all tied to a 64-Bit AMBA AHB bus. Its memory subsystem is particularly adapted to the high bandwidth demands of the multi-core architecture by providing several DMA capabilities and multiple data transfer paths. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system costs. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, operates at 145 MHz, and comsumes 3.5 Watts.
- Organisation(s)
-
Institute of Microelectronic Systems
- Type
- Paper
- Pages
- 55-61
- No. of pages
- 7
- Publication date
- 27.09.2003
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- Computer Science Applications, Hardware and Architecture, Electrical and Electronic Engineering
- Electronic version(s)
-
https://doi.org/10.1145/1152923.1024303 (Access:
Closed)
