A scalable packet sorting circuit for high-speed WFQ packet scheduling
- authored by
- K. McLaughlin, S. Sezer, H. Blume, X. Yang, F. Kupzog, T. Noll
- Abstract
A novel implementation of a tag sorting circuit for a Weighted Fair Queuing (WFQ) enabled IP packet scheduler is presented. The design consists of a search tree, matching circuitry and a custom memory layout. The implementation uses 130nm silicon technology and supports Quality of Service on networks at line speeds of 40Gbps.
- External Organisation(s)
-
RWTH Aachen University
Queen's University Belfast
- Type
- Conference contribution
- Pages
- 271-274
- No. of pages
- 4
- Publication date
- 15.01.2007
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic version(s)
-
https://doi.org/10.1109/SOCC.2006.283896 (Access:
Closed)
