Leibniz Universität Hannover Faculty Faculty of Electrical Engineering and Computer Science
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Institute of Microelectronic Systems
 
Institute of Microelectronic Systems Studies Courses

Lab: FPGA Design Technology

The Lab: FPGA Design Technology covers the contents of the lecture FPGA Design Technology in practical experiments by audio signal processing on an FPGA. The processing of the tasks is done by interactive self-study in groups.

Entwurf eines Audio-Effektgerätes im Labor „FPGA-Entwurfstechnik” Entwurf eines Audio-Effektgerätes im Labor „FPGA-Entwurfstechnik” Entwurf eines Audio-Effektgerätes im Labor „FPGA-Entwurfstechnik” © IMS

Content

The Upper School Lab is offered once a year during the winter semester.
The course is designed for students in the master's program and accompanies the lecture: FPGA Design Technology.

The goal is to develop an FPGA-based audio effect device with an expandable concept. Thus, the audio effect device can be used to read in own music, process it and output it, for example, with a reverb effect and volume control. Development takes place in sequential experiments, introducing students to concepts of the hardware description language VHDL and digital audio signal processing. The learning progress is checked by means of tests.

The experiments are carried out in group work in presence. The FPGA board can be taken home for independent learning. The software tools required for the processing are publicly available as free versions. (Modelsim, Quartus)

Registration

Laboratory places are allocated via the central laboratory registration system of the Faculty of Electrical Engineering and Computer Science. Students of all faculties have to register for the lab via this system.
In addition, you must register your participation in this event in Stud.IP.

Introductory event

An introductory session for the FPGA Design Technology lab will be held at the beginning of the semester in the Multimedia Lecture Hall (Room 023, Appelstraße 4, Building 3703). Material distribution and group assignment will take place there. The date and procedure will be announced in the Stud.IP event after the lab places have been allocated.

Lab room

The lab will be conducted in the eNIFE-Pool (Building 3702, 2nd floor, Room 221).

Supplementary lecture

FPGA Design Technology

Contact

FPGA-Labor
Betreuer
Email
fpga-labor@ims.uni-hannover.de
FPGA-Labor
Betreuer
Email
fpga-labor@ims.uni-hannover.de
FPGA-Lab
Stamp for successful lab participation
Phone
+49 511 762 19641
Address
Sekretariat IMS-AS
Raum 341, Appelstr.4, 3.OG
FPGA-Lab
Stamp for successful lab participation
Phone
+49 511 762 19641
Address
Sekretariat IMS-AS
Raum 341, Appelstr.4, 3.OG

Last Change: 17.05.23 Print

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