A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling
- authored by
- K. McLaughlin, S. Sezer, H. Blume, X. Yang, F. Kupzog, T. Noll
- Abstract
A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
- External Organisation(s)
-
Queen's University Belfast
RWTH Aachen University
- Type
- Article
- Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Volume
- 16
- Pages
- 781-791
- No. of pages
- 11
- ISSN
- 1063-8210
- Publication date
- 07.2008
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- Software, Hardware and Architecture, Electrical and Electronic Engineering
- Electronic version(s)
-
https://doi.org/10.1109/TVLSI.2008.2000323 (Access:
Closed)
